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PDF SPEAr320 Data sheet ( Hoja de datos )
| Número de pieza | SPEAr320 | |
| Descripción | SPEAr Embedded Microprocessors | |
| Fabricantes | ST Microelectronics | |
| Logotipo |  |
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SPEAr320
Embedded MPU with ARM926 core
for factory automation and consumer applications
Preliminary data
Features
■ ARM926EJ-S 333 MHz core
■ High-performance 8-channel DMA
■ Dynamic power-saving features
■ Configurable peripheral functions multiplexed
on 102 shared I/Os
■ Memory:
– 32 KB ROM and 8 KB internal SRAM
– LPDDR-333/DDR2-666 external memory
interface
– SDIO/MMC card interface
– Serial SPI Flash interface
– Flexible static memory controller (FSMC)
up to 16-bit data bus width, supporting
NAND Flash
– External memory interface (EMI) up to 16-
bit data bus width, supporting NOR Flash
and FPGAs
■ Security
– C3 Cryptographic accelerator
■ Connectivity
– 2 x USB 2.0 Host
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– 1 x USB 2.0 Device
– 2 x fast Ethernet MII/SMII ports
– 2 x CAN interface
– 3 x SPI
– 2 x I2C
– 1 x I2S
– 1 x fast IrDA interface
– 3 x UART interface
– 1 x standard parallel device port
■ Peripherals supported
– TFT/STN LCD controller (resolution up to
1024 x 768 and up to 24 bpp)
– Touchscreen support
■ Miscellaneous functions
LFBGA289 (15 x 15 x 1.7 mm)
– Integrated real time clock, watchdog, and
system controller
– 8-channel 10-bit ADC, 1 Msps
– 4 x PWM timers
– JPEG CODEC accelerator
– 6 x 16-bit general purpose timers with and
programmable prescaler, 4 capture inputs
– Up to 102 GPIOs with interrupt capability
Applications
The SPEAr320 embedded MPU is configurable
for a range industrial and consumer applications
such as:
■ Programmable logic controllers
■ Factory automation
■ Printers
Table 1. Device summary
Order code
Temp
range, °C
Package Packing
SPEAR320-2 -40 to 85
LFBGA289
(15 x 15 mm,
pitch 0.8 mm)
Tray
November 2009
Doc ID 16755 Rev 1
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to
change without notice.
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1 page  
SPEAr320
1 Description
Description
The SPEAr320 is a member of the SPEAr family of embedded MPUs, optimized for
industrial automation and consumer applications. It is based on the powerful ARM926EJ-S
processor (up to 333 MHz), widely used in applications where high computation
performance is required.
In addition, SPEAr320 has an MMU that allows virtual memory management -- making the
system compliant with Linux operating system. It also offers 16 KB of data cache, 16 KB of
instruction cache, JTAG and ETM (Embedded Trace Macrocell™) for debug operations.
A full set of peripherals allows the system to be used in many applications, some typical
applications being factory automation, printer and consumer applications.
Figure 1. Functional block diagram
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Doc ID 16755 Rev 1
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5 Page 
SPEAr320
Architecture overview
The Figure 3 shows the typical SMII configuration (a generic example with four ports):
Figure 3. Typical SMII system
8
port
MAC
4 Tx
4 Rx
Sync
Clock
4 Tx
4 Rx
Sync
Quad
PHY
Quad
PHY
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Each Ethernet port provides the following features:
● Compatible with IEEE Standard 802.3
● 10 and 100 Mbit/s operation
● Full and half duplex operation
● Statistics counter registers for RMON/MIB
● Interrupt generation to signal receive and transmit completion
● Automatic pad and CRC generation on transmitted frames
● Automatic discard of frames received with errors
● Address checking logic supports up to four specific 48-bit addresses
● Supports promiscuous mode where all valid received frames are copied to memory
● Hash matching of unicast and multicast destination addresses
● External address matching of received frames
● Physical layer management through MDIO interface
● Supports serial network interface operation
● Half duplex flow control by forcing collisions on incoming frames
● Full duplex flow control with recognition of incoming pause frames and hardware
generation of transmitted pause frames
● Support for 802.1Q VLAN tagging with recognition of incoming VLAN and priority
tagged frames
● Multiple buffers per receive and transmit frame
● Wake on LAN support
● Jumbo frames of up to 10240 bytes supported
● Configurable Endianess for the DMA Interface (AHB Master)
Doc ID 16755 Rev 1
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| PDF Descargar | [ Datasheet SPEAr320.PDF ] | |
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