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PDF CYIL1SM0300AA Data sheet ( Hoja de datos )

Número de pieza CYIL1SM0300AA
Descripción LUPA-300 CMOS Image Sensor
Fabricantes Cypress Semiconductor 
Logotipo Cypress Semiconductor Logotipo



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CYIL1SM0300AA
LUPA-300 CMOS Image Sensor
Features
• This VGA-resolution CMOS active pixel sensor features
• Synchronous shutter.
• A maximal frame-rate of 250 fps in full resolution.
• Readout speed can be boosted by means of sub sampling
www.DataaSnhdeewt4iUnd.coowmed Region Of Interest (ROI) readout.
• High dynamic range scenes can be captured using the
double and triple slope functionality.
• User programmable row and column start/stop positions
allow windowing and sub sampling
• Reduces resolution while maintaining the constant field of
view and an increased frame rate.
• The programmable gain and offset amplifier maps the signal
swing to the ADC input range.
• A 10-bit ADC converts the analog data to a 10-bit digital
word stream.
• Sensor uses a 3-wire Serial-Parallel (SPI) interface.
• Sensor operates with a 3.3V and 2.5V power supply and
requires only one master clock for operation up to 80 MHz
pixel rate.
• Available in a 48-pin ceramic LCC package.
• The sensor is available in a Monochrome version or Bayer
(RGB) patterned color filter array.
Applications
• Machine vision
• Motion tracking
Parameter
Optical Format
Active Pixels
Pixel Size
Shutter Type
Maximum Data Rate/Master
Clock
Frame Rate
ADC Resolution
Responsivity
Dynamic Range
Supply Voltage
Power Consumption
Operating Temperature
Color Filter Array
Packaging
Typical View
½ inch
640 (H) x 480 (V)
9.9 µm x 9.9 µm
Electronic Snapshot Shutter
80 MPS/80 MHz
250 fps (640 x 480)
10-bit, on-chip
3200 V.m2/W.s
17 V/lux.s
61 dB
Analog: 2.5V-3.3V
Digital: 2.5V
I/O: 2.5V
190 mWatt
–40C to 70C
Mono
RGB Bayer Pattern
48-pins LCC
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document Number: 001-00371 Rev. *D
Revised January 2, 2007
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CYIL1SM0300AA pdf
CYIL1SM0300AA
Specifications
General Specifications
Table 1. General Specification
Parameter
Specifications
Pixel Architecture
Pixel Size
Resolution
Pixel Rate
Shutter Type
Frame Rate
6 transistor pixel
9.9 µm x 9.9 µm
640 x 480
80 MHz
Pipelined snapshot shutter
250 fps
Remarks
The pixel size and resolution result in a 6.3 mm x 4.7 mm optical
active area (1/2 inch).
Integration during read out is possible
Frame rate can be boosted by sub sampling and windowing
Electro-Optical Specifications
Overview
Table 2. Electro-Optical Specifications
Parameter
FPN
PRNU
Conversion gain
Saturation charge
Sensitivity
Peak QE * FF
Dark current (@ 21 °C)
Noise electrons
S/N ratio
www.DatPaSahraeseitt4icU.sceonmsitivity
MTF
Power dissipation
Typical Specifications
2.5% RMS
2.5% RMS
34 uV/e-
35.000 e-
3200 V.m2/W.s
17V/lux.s
45%
300mV/s
32e-
60.7 dB
1/5000
60%
160 mW
190 mW
Remarks
10% peak-to-peak, min: NA, max: 3.1%
min:NA, max: 3.1%
@ output, min: NA, max: NA
min: NA, max: NA
min: NA, max: NA
Visible band only (180 lux = 1 W/m2)
min: NA, max: NA
min: NA, max: NA
min: NA, max: NA
min: NA, max: NA
min:NA, max: NA
Typical, not including output load
Typical, including output loads of 15 pF
Document Number: 001-00371 Rev. *D
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CYIL1SM0300AA arduino
CYIL1SM0300AA
by the register FT_TIMER. Section 3.1 explains the use of this
register.
Table 7. Typical frame rates for 80-MHz clock and
GRAN<1:0>=10
Image
resolution
(X * Y)
Frame rate
Frame
(fps)
readout (us)
Comment
640 x 480
247.5
4038
640 x 240
488.3
2048
sub sampling
256 x 256
1076
929 windowing
Analog to Digital Converter
The sensor has four 10-bit pipelined ADC on board. The ADCs
are nominally operating at 20 Msamples/s. The input range of
the ADC is between 0.75 and 1.75V. The analog input signal
is sampled at 2.1 ns delay from the rising edge of the ADC
clock.
The digital output data appears at the output at 5.5 cycles later.
This is at the 6th falling edge succeeding the sample moment.
The data is delayed by 3.7 ns with respect to this falling edge.
This is illustrated in Figure 5.
Figure 5. ADC Timing
CLK_ADC
50ns
ADC_IN
D1 D2 D3 D4 D5 D6 D7 D8
ADC_OUT
<9:0>
DUMMY
5.5 clock cycles
D1 D2 D3 D4
3.7ns
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Table 8. ADC Parameters
Parameter
Specification
Data rate
20 Msamples/s
Input range
0.75V - 1.75 V
Quantization
10 bit
DNL
Typ. < 0.3 LSB
INL Typ. < 0.7 LSB
Programmable Gain Amplifiers
The programmable gain amplifiers have two functions:
Adding an offset to the signal to fit it into the range of the ADC.
This is controlled by the VBLACK and VOFFSET SPI settings.
Amplifying the signal after the offset has been added.
Offset Regulation
The purpose of the offset regulation is to bring the signal in the
input range of the ADC.
After the column amplifiers the signal from the pixels has a
range from 0.1V (bright) to 1.3V (black). The input range of the
ADC is from 0.75V to 1.75V. The amount of offset added is
controlled by two SPI settings: VBLACK<7:0> and
VOFFSET<7:0>. The formula for adding offset is:
Voutput = Vsignal + (Voffset - Vblack)
One should know that the FPN (fixed pattern noise) of the
sensor causes a spread of about 100 mV on the dark level. To
allow FPN correction during post processing of the image, this
spread on the dark level needs to be covered by the input
range of the ADC. This is the reason why the default settings
of the SPI are programmed to add an offset of 200 mV. This
way the dark level goes from 1.3V to 1.5V and is the FPN
information still converted by the ADC. To even better match
the ADC range we advice to program a offset of 340 mV. To
program this offset the Voffset and Vblack registers can be
used. See section 3.8 for more explanation. Figure 6 illus-
trates the operation of the offset regulation with an example.
The blue histogram is the histogram of the image taken after
the column amplifiers. Let's say the device has a black level of
Document Number: 001-00371 Rev. *D
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