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PDF DS92LV3221 Data sheet ( Hoja de datos )
| Número de pieza | DS92LV3221 | |
| Descripción | (DS92LV3221 / DS92LV3222) 20-50 MHz 32-Bit Channel Link II Serializer/Deserializer | |
| Fabricantes | National Semiconductor Corporation | |
| Logotipo |  |
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DS92LV3221/DS92LV3222
October 21, 2009
20-50 MHz 32-Bit Channel Link II Serializer/Deserializer
General Description
The DS92LV3221 (SER) serializes a 32-bit data bus into 2
embedded clock LVDS serial channels for a data payload rate
up to 1.6 Gbps over cables such as CATx, or backplanes FR-4
traces. The companion DS92LV3222 (DES) deserializes the
2 LVDS serial data channels, de-skews channel-to-channel
delay variations and converts the LVDS data stream back into
a 32-bit LVCMOS parallel data bus.
On-chip data Randomization/Scrambling and DC balance en-
coding and selectable serializer Pre-emphasis ensure a ro-
bust, low-EMI transmission over longer, lossy cables and
backplanes. The Deserializer automatically locks to incoming
data without an external reference clock or special sync pat-
terns, providing an easy “plug-and-lock” operation.
By embedding the clock in the data payload and including
signal conditioning functions, the Channel-Link II SerDes de-
vices reduce trace count, eliminate skew issues, simplify
design effort and lower cable/connector cost for a wide variety
of video, control and imaging applications. A built-in AT-
SPEED BIST feature validates link integrity and may be used
for system diagnostics.
Features
■ Wide Operating Range Embedded Clock SER/DES
— Up to 32-bit parallel LVCMOS data
— 20 to 50 MHz parallel clock
— Up to 1.6 Gbps application data paylod
■ Simplified Clocking Architecture
— No separate serial clock line
— No reference clock required
— Receiver locks to random data
■ On-chip Signal Conditioning for Robust Serial
Connectivity
— Transmit Pre-Emphasis
— Data randomization
— DC-balance encoding
— Receive channel deskew
— Supports up to 10m CAT-5 at 1.6Gbps
■ Integrated LVDS Terminations
■ Built-in AT-SPEED BIST for end-to-end system testing
■ AC-coupled interconnect for isolation and fault protection
■ > 4KV HBM ESD protection
■ Space-saving 64-pin TQFP package
■ Full industrial temperature range : -40° to +85°C
Applications
■ Industrial imaging (Machine-vision) and control
■ Security & Surveillance cameras and infrastructure
■ Medical imaging
www.DaBtalSohecekt4UD.coiamgram
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 2009 National Semiconductor Corporation 301057
30105727
www.national.com
1 page  
DS92LV3222 Deserializer Pin Descriptions
Pin #
Pin Name
I/O, Type
Description
LVCMOS PARALLEL INTERFACE PINS
5–7,
10–14,
19–25,
28–32,
33–39,
42–46
RxOUT[31:29],
RxOUT[28:24],
RxOUT[23:17],
RxOUT[16:12],
RxOUT[11:5],
RxOUT[4:0]
O, LVCMOS Deserializer Parallel Interface Data Output Pins.
4
RxCLKOUT
O, LVCMOS Deserializer Recovered Clock Output. Parallel data rate clock recovered from the embedded
clock.
3 LOCK
O, LVCMOS LOCK indicates the status of the receiver PLL LOCK = L; deserializer CDR/PLL is not locked,
RxOUT[31:0] and RCLK are TRI-STATED®
LOCK = H; deserializer CDR/PLL is locked
CONTROL AND CONFIGURATION PINS
48 R_FB
I, LVCMOS
Rising/Falling Bar Clock Edge Select
R_FB = H; RxOUT clocked on rising edge
R_FB = L; RxOUT clocked on falling edge
50 REN
I, LVCMOS
Deserializer Enable, DES Output Enable Control Input (ACTIVE HIGH)
REN = L; disabled, RxOUT[31:0] and RxCLKOUT TRI-STATED, PLL still operational
REN = H; Enabled (ACTIVE HIGH)
49 PDB
I, LVCMOS
Power Down Bar, Control Input Signal (ACTIVE LOW)
PDB = L; disabled, RxOUT[31:0], RCLK, and LOCK are TRI-STATED in stand-by mode,
PLL is shutdown
PDB = H; Enabled
47 RSVD
I, LVCMOS Reserved — MUST BE TIED LOW
57, 58, NC
59, 60
Do Not Connect, leave pins floating
LVDS SERIAL INTERFACE PINS
51, 53 RxIN[0:1]+
I, LVDS
Deserializer LVDS Non-Inverted Inputs(+)
52, 54 RxIN[0:1]-
I, LVDS
Deserializer LVDS Inverted Inputs(-)
POWER / GROUND PINS
9, 16, VDD
17, 26,
6w1ww.DataSheet4U.com
VDD
Digital Voltage supply, 3.3V
8, 15, VSS
18, 27,
62
GND
Digital Ground
55 VDDA
VDD
Analog LVDS Voltage supply, POWER, 3.3V
56 VSSA
GND
Analog LVDS GROUND
1, 40, 64 VDDPLL
VDD
Analog Voltage supply PLL VCO POWER, 3.3V
2, 41, 63 VSSPLL
GND
Analog ground, PLL VCO GROUND
5 www.national.com
5 Page 
FIGURE 7. Serializer PLL Lock Time
30105733
30105748
FIGURE 8. Deserializer LVCMOS Output Transition Time
www.DataSheet4U.com
FIGURE 9. Deserializer Setup and Hold times
30105734
FIGURE 10. Deserializer Propagation Delay
11
30105746
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11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet DS92LV3221.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| DS92LV3221 | DS92LV3221/3222 20-50 MHz 32-Bit Channel Link II Serializer / Deserializer (Rev. C) |  Texas Instruments |
| DS92LV3221 | (DS92LV3221 / DS92LV3222) 20-50 MHz 32-Bit Channel Link II Serializer/Deserializer | National Semiconductor Corporation |
| DS92LV3222 | DS92LV3221/3222 20-50 MHz 32-Bit Channel Link II Serializer / Deserializer (Rev. C) | Texas Instruments |
| DS92LV3222 | (DS92LV3221 / DS92LV3222) 20-50 MHz 32-Bit Channel Link II Serializer/Deserializer | National Semiconductor Corporation |
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