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PDF LTC2470 Data sheet ( Hoja de datos )
| Número de pieza | LTC2470 | |
| Descripción | (LTC2470 / LTC2472) System Monitoring | |
| Fabricantes | Linear Technology | |
| Logotipo |  |
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LTC2470/LTC2472
FEATURES
Selectable 250sps/1ksps,
16-Bit ΔΣ ADCs with 10ppm/°C
Max Precision Reference
DESCRIPTION
n 16-Bit Resolution, No Missing Codes
n Internal, High Accuracy Reference—10ppm/°C (Max)
n Single-Ended (LTC2470) or Differential (LTC2472)
n Selectable 250sps/1ksps Output Rate
n 1mV Offset Error
n 0.01% Gain Error
n Single Conversion Settling Time for Multiplexed
Applications
n Single-Cycle Operation with Auto Shutdown
n 3.5mA (Typ) Supply Current
n 2μA (Max) Sleep Current
n Internal Oscillator—No External Components
Required
n SPI Interface
n Small 12-Lead, 3mm × 3mm DFN and MSOP
Packages
APPLICATIONS
n System Monitoring
n Environmental Monitoring
n Direct Temperature Measurements
n Instrumentation
wwwn.DaItnaSdhuesettr4iUa.lcPomrocess Control
n Data Acquisition
n Embedded ADC Upgrades
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
Protected by U.S. Patents, including 6208279, 6411242, 7088280, 7164378.
The LTC®2470/LTC2472 are small, 16-bit analog-to-digital
converters with an integrated precision reference and
a selectable 250sps or 1ksps output rate. They use a
single 2.7V to 5.5V supply and communicate through a
SPI Interface. The LTC2470 is single-ended with a 0V to
VREF input range and the LTC2472 is differential with a
±VREF input range. Both ADC’s include a 1.25V integrated
reference with 2ppm/°C drift performance and 0.1% initial
accuracy. The converters are available in a 12-pin DFN
3mm × 3mm package or an MSOP-12 package. They
include an integrated oscillator and perform conver-
sions with no latency for multiplexed applications. The
LTC2470/LTC2472 include a proprietary input sampling
scheme that reduces the average input current several
orders of magnitude when compared to conventional
delta sigma converters.
Following a single conversion, the LTC2470/LTC2472
automatically power down the converter and can also be
configured to power down the reference. When both the
ADC and reference are powered down, the supply current
is reduced to 200nA.
The LTC2470/LTC2472 include a user selectable 250sps
or 1ksps output rate and due to a large oversampling
ratio (8,192 at 250sps and 2,048 at 1ksps) have relaxed
anti-aliasing requirements.
TYPICAL APPLICATION
2.7V TO 5.5V
0.1μF
0.1μF
0.1μF
10μF
0.1μF
REFOUT
COMP VCC
10k 10k
IN+ SCK
IN–
LTC2472
SDO
CS
SPI
INTERFACE
10k
R
0.1μF
REF–
GND
24702 TA01a
VREF vs Temperature
1.2520
1.2515
1.2510
1.2505
1.2500
1.2495
1.2490
1.2485
1.2480
–50 –30 –10 10 30 50
TEMPERATURE (°C)
70 90
24702 TA01b
24702f
1
1 page  
LTC2470/LTC2472
TYPICAL PERFORMANCE CHARACTERISTICS (TA = 25°C, unless otherwise noted)
Integral Nonlinearity
3
VCC = 2.7V
TA = –45°C, 25°C, 90°C
2 OUTPUT RATE = 250sps
1
0
–1
–2
–3
–1.25
–0.75 –0.25 0.25 0.75 1.25
DIFFERENTIAL INPUT VOLTAGE (V)
24702 G01
Integral Nonlinearity
3
2
1
0
–1
–2 VCC = 5.5V
TA = –45°C, 25°C, 90°C
OUTPUT RATE = 250sps
–3
–1.25 –0.75 –0.25 0.25 0.75 1.25
DIFFERENTIAL INPUT VOLTAGE (V)
24702 G02
Maximum INL vs Temperature
6 OUTPUT RATE = 250sps
4
VCC = 5.5V
2
VCC = 4.1V
0
–2 VCC = 2.7V
–4
–6
–50 –30 –10 10 30 50
TEMPERATURE (°C)
70 90
24702 G03
Offset Error vs Temperature
35
30
VCC = 5.5V
25
20
15 VCC = 4.1V
10
VCC = 2.7V
5
www.DataS0heet4U.com
–50 –30 –10 10 30 50
TEMPERATURE (°C)
70 90
24702 G04
Conversion Mode Power Supply
Current vs Temperature
4.0
3.9
VCC = 5.5V
3.8
3.7
VCC = 4.1V
3.6
3.5
3.4
VCC = 2.7V
3.3
3.2
3.1
3.0
–50 –30 –10 10 30 50
TEMPERATURE (°C)
70 90
24702 G07
ADC Gain Error vs Temperature
50
40
VCC = 5.5V
30
20
10 VCC = 4.1V
0
VCC = 2.7V
–10
–50 –30
–10 10 30 50
TEMPERATURE (°C)
70 90
24702 G05
Transition Noise vs Temperature
10
9
8
7
6 VCC = 5.5V
5
4
3
VCC = 2.7V
2
1
0
–50 –30 –10 10 30 50
TEMPERATURE (°C)
70 90
24702 G06
Sleep Mode Power Supply
Current vs Temperature
350
300
VCC = 5.5V
250
200
150 VCC = 4.1V
100
50 VCC = 2.7V
0
–50 –30 –10 10 30 50
TEMPERATURE (°C)
70 90
24702 G08
VREF vs Temperature
1.2508
1.2507
1.2506
1.2505
1.2504
1.2503
1.2502
–50 –30 –10 10 30 50
TEMPERATURE (°C)
70 90
24702 G09
24702f
5
5 Page 
LTC2470/LTC2472
APPLICATIONS INFORMATION
The speed bit (SPD) determines the output rate, SPD = 0
(default) for a 250sps and SPD = 1 for a 1ksps output
rate. The sleep bit (SLP) is used to power down the
on-chip reference. In the default mode, the reference re-
mains powered up at the conclusion of each conversion
cycle while the ADC is automatically powered down at the
end of each conversion cycle. If the SLP bit is set HIGH,
the reference and the ADC are powered down once the
next conversion cycle is completed. The reference and
ADC are powered up again once CS is pulled low. The
following conversion is invalid if the next conversion is
started before the reference has started up (see Figure 3
for reference startup times as a function of compensation
capacitor and reference capacitor).
If the sleep mode is not required, SPD can be tied to GND
or VDD in order to simplify the user interface. It should
be noted that by tying SDI to GND, the output rate will
be set to 250sps. Tying SDI to VDD will result in a 1ksps
output rate.
SERIAL INTERFACE
The LTC2470/LTC2472 transmit the conversion result
and receive the start of conversion command through
a synchronous 2-, 3- or 4-wire interface. This interface
can be used during the DATA OUTPUT state to read the
wwwc.DoantavSehreseiot4nU.rceosmult, program sleep and speed mode, and
to trigger a new conversion.
Serial Interface Operation Modes
The modes of operation can be summarized as follows:
1) The LTC2470/LTC2472 function with SCK idle high
(commonly known as CPOL = 1) or idle low (commonly
known as CPOL = 0).
2) After the 16th bit is read, a new conversion is started
if CS is pulled high or SCK is pulled low.
3) At any time during the Data Output state, pulling CS
high causes the part to leave the I/O state, abort the
output and begin a new conversion.
Serial Clock Idle-High (CPOL = 1) Examples
In Figure 6, following a conversion cycle the LTC2470/
LTC2472 automatically enter the NAP mode with the ADC
powered down. The ADC’s reference will power down if the
SLP bit was set high prior to the just completed conversion
and CS is HIGH. Once CS goes low, both the reference and
ADC are powered up.
When the conversion is complete, the user applies 16
clock cycles to transfer the result. The CS rising edge is
then used to initiate a new conversion.
The operation example of Figure 7 is identical to that of
Figure 6, except the new conversion cycle is triggered by
the falling edge of the serial clock (SCK).
CS
SD0
SCK
SDI
CONVERT
D15 D14 D13 D12 D2 D1 D0
clk1 clk2 clk3 clk4
clk15 clk16
EN1 EN2 SPD SLP
NAP DATA OUTPUT
Figure 6. Idle-High (CPOL = 1) Serial Clock Operation Example.
The Rising Edge of CS Starts a New Conversion
CONVERT
24702 F06
24702f
11
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet LTC2470.PDF ] | |
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