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PDF CP3SP33 Data sheet ( Hoja de datos )
| Número de pieza | CP3SP33 | |
| Descripción | Connectivity Processor | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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PRELIMINARY
September 2005
CP3SP33 Connectivity Processor with Cache, DSP, and
Bluetooth®, USB, and Dual CAN Interfaces
1.0 General Description
The CP3SP33 connectivity processor combines high per-
formance with the massive integration needed for embed-
ded Bluetooth applications. A powerful RISC core with 4K-
byte instruction cache and a Teak® DSP coprocessor pro-
vides high computing bandwidth, DMA-driven hardware
communications peripherals provide high I/O bandwidth,
and an external bus provides system expandability.
On-chip communications peripherals include: Bluetooth
Lower Link Controller, Universal Serial Bus (2.0) OTG node
and host controller, dual CAN, dual Microwire/Plus/SPI,
dual ACCESS.bus, quad UART, 10-bit A/D converter, and
telematics/audio codec. Additional on-chip peripherals in-
clude DMA controller, dual CVSD/PCM conversion module,
I2S and AAI digital audio bus interfaces, Timing and Watch-
dog Unit, dual Versatile Timer Unit, dual Multi-Function Tim-
er, and Multi-Input Wake-Up (MIWU) unit.
In addition to providing the features needed for the next gen-
eration of embedded Bluetooth products, the CP3SP33 is
backed up by the software resources that designers need
for rapid time-to-market, including an operating system,
Bluetooth protocol stack implementation, peripheral drivers,
reference designs, and an integrated development environ-
ment. Combined with an external program memory and a
Bluetooth radio transceiver such as National’s LMX5252,
the CP3SP33 provides a complete Bluetooth system solu-
tion.
National Semiconductor offers a complete and industry-
proven application development environment for CP3SP33
applications, including the IAR Embedded Workbench,
iSYSTEM winIDEA and iC3000 Active Emulator, Bluetooth
Development Board, Bluetooth protocol stack, and applica-
tion examples.
Block Diagram
www.DataSheet4U.com
Bluetooth is a registered trademark of Bluetooth SIG, Inc. and is used under license by National Semiconductor. Teak is a registered trademark of ParthusCeva, Inc.
TRI-STATE is a registered trademark of National Semiconductor Corporation.
©2005 National Semiconductor Corporation
www.national.com
1 page  
3.16 DUAL ACCESS.BUS INTERFACE
3.21 POWER MANAGEMENT
The two ACCESS.bus (ACB) interface modules support a
two-wire serial interface compatible with the ACCESS.bus
physical layer. It is also compatible with Intel’s System Man-
agement Bus (SMBus) and Philips’ I2C bus. The ACB mod-
ules can be configured as a bus master or slave, and they
can maintain bidirectional communications with both multi-
ple master and slave devices.
The ACCESS.bus receivers can trigger a wake-up condition
out of the low-power modes through the Multi-Input Wake-
Up module.
3.17 DUAL MULTI-FUNCTION TIMER
The two Multi-Function Timer (MFT) modules each contain
a pair of 16-bit timer/counter registers. Each timer/counter
unit can be configured to operate in any of the following
modes:
— Processor-Independent Pulse Width Modulation
(PWM) mode: Generates pulses of a specified width
and duty cycle and provides a general-purpose timer/
counter.
— Dual Input Capture mode: Measures the elapsed time
between occurrences of external event and provides
a general-purpose timer/counter.
— Dual Independent Timer mode: Generates system
timing signals or counts occurrences of external
events.
— Single Input Capture and Single Timer mode: Pro-
vides one external event counter and one system tim-
er.
3.18 VERSATILE TIMER UNITS
The two Versatile Timer Unit (VTU) modules each contain
four independent timer subsystems, which operate as a
dual 8-bit PWM configuration, a single 16-bit PWM timer, or
a 16-bit counter with two input capture channels. Each of
the timer subsystems offer an 8-bit clock prescaler to ac-
commodate a wide range of frequencies.
www.DataSh3e.e1t94U.comTIMING AND WATCHDOG MODULE
The Timing and Watchdog Module (TWM) contains a Real-
Time timer and a Watchdog unit. The Real-Time Clock Tim-
ing function can be used to generate periodic real-time
based system interrupts. The timer output is one of 16 in-
puts to the Multi-Input Wake-Up module which can be used
to exit from a low-power mode. The Watchdog unit is de-
signed to detect the application program getting stuck in an
infinite loop resulting in loss of program control or “runaway”
programs. When the watchdog triggers, it resets the device.
The TWM is clocked by the low-speed Slow Clock.
3.20 MULTI-INPUT WAKE-UP
The Multi-Input Wake-Up (MIWU) feature is used to return
(wake-up) the device from low-power modes to the active
mode. The 64-channel MIWU unit receives wake-up signals
from various internal and external sources. In addition to the
wake-up function, the MIWU unit can generate up to eight
interrupt requests. Each MIWU channel can be individually
programmed to activate one of the interrupt requests.
The Power Management Module (PMM) improves the effi-
ciency of the device by changing the operating mode and
power consumption to match the required level of activity.
The device can operate in any of four power modes:
— Active: The device operates at full speed using the
high-frequency clock. All device functions are fully op-
erational.
— Power Save: The device operates at reduced speed
using the Slow Clock. The CPU and some modules
can continue to operate at this low speed.
— Idle: The device is inactive except for the Power Man-
agement Module and Timing and Watchdog Module,
which continue to operate using the Slow Clock.
— Halt: The device is inactive but still retains its internal
state (RAM and register contents).
The PMM provides a mechanism to handle Bluetooth-spe-
cific power management modes, for optimizing power con-
sumption during special Bluetooth states, like Park, Page
Scan, Inquiry Scan, etc.
3.22 INPUT/OUTPUT PORTS
The device has 64 software-configurable I/O pins (36 in the
FBGA-144 package), organized into four ports called Port
E, Port F, Port G, and Port H. Each pin can be configured to
operate as a general-purpose input or general-purpose out-
put. In addition, many I/O pins can be configured to operate
as inputs or outputs for on-chip peripheral modules such as
the UARTs or timers.
The I/O pin characteristics are fully programmable. Each pin
can be configured to operate as a TRI-STATE output, push-
pull output, weak pullup/pulldown input, high-speed drive, or
high-impedance input.
3.23 CLOCK AND RESET MODULE
The Clock and Reset module generates a 12-MHz Main
Clock from an external crystal network or external clock in-
put. Main Clock may be used as a reference clock for two
PLL-based clock multipliers available for generating higher-
speed clocks.
Most modules operate from clocks derived from Main Clock
or a PLL clock. Modules on the CPU core AHB bus operate
from HCLK Clock, while modules on the peripheral APB
buses operate from PCLK Clock. PCLK Clock is generated
by dividing HCLK Clock by 1, 2, or 4. Some peripheral mod-
ules may use one of several auxiliary clocks, which also are
derived from Main Clock or a PLL clock using 12-bit pro-
grammable prescalers.
In Power-Save mode, HCLK Clock is driven by Slow Clock,
which is typically a 32.768 kHz signal generated from an ex-
ternal clock network or a prescaled Main Clock may be used
to eliminate the 32.768 kHz crystal network, for the most
cost-sensitive applications. In the most power-sensitive ap-
plications, operation from an external 32.768 kHz crystal
network allows the high-frequency oscillator and PLLs to be
shut down.
5 www.national.com
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| PDF Descargar | [ Datasheet CP3SP33.PDF ] | |
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