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PDF SPEAr310 Data sheet ( Hoja de datos )
| Número de pieza | SPEAr310 | |
| Descripción | Embedded Microprocessors | |
| Fabricantes | ST Microelectronics | |
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SPEAr310
Embedded MPU with ARM926 core, flexible memory support,
extended set of powerful connectivity features
Features
■ ARM926EJ-S 333 MHz core
■ High-performance 8-channel DMA
■ Dynamic power-saving features
■ Configurable peripheral functions multiplexed
on 102 shared I/Os
■ Memory:
– 32 KB ROM and 8 KB internal SRAM
– LPDDR-333/DDR2-666 external memory
interface
– Serial SPI Flash interface
– Flexible static memory controller (FSMC)
up to 16-bit data bus width, supporting
NAND Flash
– External memory interface (EMI) up to 32-
bit data bus width, supporting NOR Flash
and FPGAs
■ Connectivity
– 2 x USB 2.0 Host
– USB 2.0 Device
– 1 x fast Ethernet MII port
– 4 x fast Ethernet SMII ports
www.DataShee–t4U1.coxmSPI, I2C and IrDA interfaces
– 6 x UART interfaces
– 1x TDM/E1 HDLC interface with 128/32
timeslots per frame respectively
– 2x RS485 HDLC ports
■ Security
– C3 Cryptographic accelerator
■ Miscellaneous functions
– Integrated real time clock, watchdog, and
system controller
– 8-channel 10-bit ADC, 1 Msps
– JPEG CODEC accelerator
– Six 16-bit general purpose timers with and
programmable prescaler, 4 capture inputs
– Up to 102 GPIOs with interrupt capability
LFBGA289 (15 x 15 x 1.7 mm)
Applications
The SPEAr310 embedded MPU is configurable
for a range of telecom and networking
applications such as:
■ Routers, switches and gateways
■ Remote apparatus control
■ Metering concentrators
Table 1. Device summary
Order code
Temp
range, °C
Package Packing
SPEAR310-2 -40 to 85
LFBGA289
(15x15 mm,
pitch 0.8 mm)
Tray
October 2009
Doc ID 16482 Rev 1
1/62
www.st.com
62
1 page  
SPEAr310
1 Description
Description
The SPEAr310 is a member of the SPEAr family of embedded MPUs, optimized for telecom
applications. It is based on the powerful ARM926EJ-S processor (up to 333 MHz), widely
used in applications where high computation performance is required.
In addition, SPEAr310 has an MMU that allows virtual memory management -- making the
system compliant with Linux operating system. It also offers 16 KB of data cache, 16 KB of
instruction cache, JTAG and ETM (embedded trace macro-cell) for debug operations.
A full set of peripherals allows the system to be used in many applications, some typical
applications being HMI, Security and VOIP phones.
Figure 1. Functional block diagram
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Doc ID 16482 Rev 1
5/62
5 Page 
SPEAr310
Architecture overview
The internal HDLC controller can service up to 128 Tx/Rx channels simultaneously in
conventional HDLC mode and supports super-channel configuration. Each channel bit rate
is programmable from 4 kbit/s to 64 kbit/s. The maximum bit rate of the TDM interface is 8
Mbps.
2.8.1
TDM interface
Main features:
● Six interface signals
● Duplex Tx/Rx communication
● Up to 8 Mbps per Tx/Rx channel
● 128 timeslots per frame (125 µs)
● Supports any timeslot banding on any Tx/Rx channel
● Tx/Rx Data sending/sampling time is configurable after/on the rising/falling edge of
TxCLK/RxCLK.
● Delay between the bit 0 of TS0 and the SYNC signal is configurable (0 - up to 3 Tx/Rx
clock cycles delay)
2.8.2
E1 interface
Main features:
● Six interface signals
● Duplex Tx/Rx communication
● Up to 2 Mbps per Tx/Rx channel
● 32 timeslots / frame (125 µs)
● Supports any timeslot banding on any Tx/Rx channel
● Tx/Rx Data sending/sampling time is configurable after/on the rising/falling edge of
TxCLK/RxCLK.
● Delay between the bit 0 of TS0 and the SYNC signal is configurable (0 - up to 3 Tx/Rx
clock cycle delay)
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2.9 RS485 HDLC ports
SPEAr310 features two RS485 HDLC ports.
Main features:
● Each RS485 interface has five signals
● Supports duplex Tx/Rx communication
● Maximum Tx/Rx data rate of RS485 HDLC is 3.88M bps
● Supports collision detection and automatic frame re-transmission
● Data sending/sampling timing is configurable:
– Tx Data can be sent out after the rising/falling edge of TxCLK
– Rx Data are sampled on the rising/falling edge of RxCLK
● No clock duty cycle constraints, data sending/receiving depends only on the
rising/falling edge of Tx/Rx clock
Doc ID 16482 Rev 1
11/62
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet SPEAr310.PDF ] | |
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