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PDF SPEAr300 Data sheet ( Hoja de datos )
| Número de pieza | SPEAr300 | |
| Descripción | Embedded Microprocessors | |
| Fabricantes | ST Microelectronics | |
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SPEAr300
Embedded MPU with ARM926 core, flexible memory support,
powerful connectivity features and human machine interface
Features
■ ARM926EJ-S core up to 333 MHz
■ High-performance 8-channel DMA
■ Dynamic power-saving features
■ Configurable peripheral functions multiplexed
on 102 shared I/Os
■ Memory
– 32 KB ROM and 57 KB internal SRAM
– LPDDR-333/DDR2-666 external memory
interface
– Flexible static memory controller (FSMC)
up to 16-bit data bus width, supporting
external SRAM, NAND/NOR Flash and
FPGAs
– Serial SPI Flash interface
– SDIO/MMC card interface
■ Connectivity
– 2 x USB 2.0 Host
– USB 2.0 Device
– Fast Ethernet (MII port)
– SPI, I2C, I2S, UART and IrDA interfaces
– TDM bus (512 timeslots)
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– Up to
8
additional
I2C/SPI
chip
selects
■ Security
– C3 cryptographic accelerator
■ Peripherals supported
– Camera interface (ITU-601/656 and CSI2
support)
– TFT/STN LCD controller (resolution up to
1024 x 768 and up to 24 bpp)
– Touchscreen support
– 9 x 9 keyboard controller
– Glueless management of up to 8
SLICs/CODECs
■ Miscellaneous functions
– Integrated real time clock, watchdog, and
system controller
LFBGA289 (15 x 15 x 1.7 mm)
– 8-channel 10-bit ADC, 1 Msps
– 1-bit DAC
– JPEG codec accelerator
– Six 16-bit general purpose timers with
capture mode and programmable prescaler
– Up to 44 GPIOs
Applications
■ SPEAr300 embedded MPU is configurable in
13 sets of peripheral functions targeting a
range of applications:
– General purpose NAND Flash or NOR
Flash based devices
– Digital photo frames
– WiFi or IP phones (low end or high end)
– ATA PABX systems (with or without I2S)
– 8-bit or 14-bit camera (with or without LCD)
Table 1. Device summary
Order code
Temp
range, °C
Package
Packing
SPEAR300-2
- 40 to 85
°C
LFBGA289
(15x15 mm)
pitch 0.8
mm
Tray
October 2009
Doc ID 16324 Rev 1
1/69
www.st.com
69
1 page  
SPEAr300
1 Description
Description
The SPEAr300 is a member of the SPEAr family of embedded MPUs for networked devices.
It is based on the powerful ARM926EJ-S processor (up to 333 MHz), widely used in
applications where high computation performance is required.
In addition, SPEAr300 has an MMU that allows virtual memory management -- making the
system compliant with Linux operating system. It also offers 16 KB of data cache, 16 KB of
instruction cache, JTAG and ETM (embedded trace macro-cell) for debug operations.
A full set of peripherals allows the system to be used in many applications, some typical
applications being HMI, Security and VoIP phones.
Figure 1. Functional block diagram
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Doc ID 16324 Rev 1
5/69
5 Page 
SPEAr300
Architecture overview
2.6 Flexible static memory controller
SPEAr300 provides a Flexible Static Memory Controller (FSMC) which interface the AHB
bus to external NAND/NOR Flash memories and to asynchronous SRAM memories.
Main features:
● Provides an interface between AHB system bus and external parallel memory devices
● Interfaces static memory-mapped devices including RAM, ROM and synchronous burst
Flash.
● For SRAM and Flash 8/16-bit wide, external memory and data paths are provided
● FSMC performs only one access at a time and only one external device is accessed.
● Supports little-endian and big-endian memory architectures
● AHB burst transfer handling to reduce access time to external devices
● Supplies an independent configuration for each memory bank
● Programmable timings to support a wide range of devices
● Programmable wait states (up to 31)
● Programmable bus turnaround cycles (up to 15)
● Programmable output enable and write enable delays (up to 15)
● Provides independent chip select control for each memory bank
● Shares the address bus and the data bus with all the external peripherals. Only the chip
selects are unique for each peripheral
● External asynchronous wait control
● Boot memory bank configurable at reset using external control pins
2.7 Multichannel DMA controller
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Within its basic subsystem, SPEAr300 provides an DMA controller (DMAC) able to service
up to 8 independent DMA channels for serial data transfers between single source and
destination (i.e., memory-to-memory, memory-to-peripheral, peripheral to- memory, and
peripheral-to-peripheral).
Each DMA channel can support a unidirectional transfer, with internal four-word FIFO per
channel.
Doc ID 16324 Rev 1
11/69
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