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PDF SPEAR-09-B042 Data sheet ( Hoja de datos )
| Número de pieza | SPEAR-09-B042 | |
| Descripción | large IP portfolio SoC | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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SPEAR-09-B042
SPEAr® BASIC
ARM 926EJ-S core, customizable logic, large IP portfolio SoC
Preliminary Data
Features
■ ARM926EJ-S core @333 MHz
– 16 Kbyte instructions/data cache
■ Reconfigurable logic array:
– 300 Kgate (100% utilization rate)
– 102 I/O lines
– No clock domain limitation
– 64 Kbyte + 8 Kbyte configurable memory
pool
■ Multilayer AMBA 2.0 compliant bus with fMAX
166 MHz
■ 32-Kbyte boot ROM
■ 8 Kbyte common static RAM
– Shared with reconfigurable array
■ Dynamic power saving features
■ High performance DMA
– 8 channels
■ Ethernet 10/100 MAC with MII interface.
(IEEE-802.3)
■ USB 2.0 device with integrated PHY
■ 2 USB 2.0 host with integrated PHY
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■ External DRAM memory interface:
– 8/16-bit (LPDDR@166 MHz)
– 8/16-bit (DDR2@333 MHz)
– 2 banks available
■ Flash interface:
– SPI serial (up to 50 Mbps)
■ SPI master/slave up to 50 Mbps
– Compliant with Motorola, Texas
instruments and National semiconductor
protocols
■ I2C master/slave mode – high, fast and slow
speed
■ UARTs (up to 460.8 Kbps)
■ IrDA (FIR/MIR/SIR) compliant serial link from
9.6 Kbps to 4 Mbps speed-rate
LFBGA289
■ 6 legacy GPIO bidirectional signals with
interrupt capability
■ ADC 10-bit, 1 Msps 8 inputs
– Hw supporting up to 13.5 bits at 8 KSPS by
oversampling and accumulation
■ JPEG codec accelerator (1 clock/pixel)
■ C3 crypto accelerator
■ 3 pairs of 16-bit general purpose timers with
programmable prescaler
■ Real-time clock
■ Watchdog
■ System controller
■ Miscellaneous internal control registers
– SOC parameter configuration
■ JTAG (IEEE1149.1) interface
■ ETM9 interface
■ Operating temperature: - 40 to 85 °C
■ Low power consumption technology
Description
SPEAr BASIC is a powerful digital engine
belonging to SPEAr family, the innovative
customizable system-on-chip. The device
integrates an ARM 926 core with an extensive set
of proven IPs and a large configurable logic block
that allows very fast customization of unique
and/or proprietary solutions.
May 2008
Rev 1
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to
change without notice.
1/66
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1
1 page  
SPEAR-09-B042
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
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Table 32.
Table 33.
Table 34.
Pin description by functional group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Main memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
ICM1 – Low speed connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
ICM4 – High speed connection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
ML1 – Multi layer CPU subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
ICM3 – Basic subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Equivalent values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Equivalent values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Endpoint assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Reconfigurable logic array interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
RAS_M – communication subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
PL_CLK mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
PL_GPIO mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
KBREG coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
TDM block pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
I2S interface pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
DAC performances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Maximum picture size according data format and buffer size. . . . . . . . . . . . . . . . . . . . . . . 53
Camera interface pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Camera interface timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
TDM timing specification (1024 TS = 65536 kHz = 15.26 ns). . . . . . . . . . . . . . . . . . . . . . . 58
I2S timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Absolute maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Recommended operating condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Low voltage TTL DC input specification (3V< VDD <3.6V) . . . . . . . . . . . . . . . . . . . . . . . . . 61
Low voltage TTL DC output specification (3V< VDD <3.6V) . . . . . . . . . . . . . . . . . . . . . . . . 61
Pull-up and pull-down characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Driver characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
On die termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Reference voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
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5 Page 
SPEAR-09-B042
5 Block diagram
Figure 2. Block diagram
SPEArBASIC
Configurable Cell Array Subsystem
SRAM SRAM
16KB 16KB
CPU
ARM926EJ-S
Cache: 16kI 16kD
Coprocessor i/f
Tcm-I/D I D
ARM Subsystem
Int. Tmr
Ctr APB
Block diagram
Cell Array
(Applic. configurable)
SRAM SRAM
16KB 16KB
6
6-78 1-123
Uart
SPI
I2C
D
JPEG
(Codec)
RAM
(8KB)
ADC
IrDA
Low Speed Subsystem
1
Multi-layer Interconnection Matrix
2-12(4)
6
3-12 3 4
4-12 7 8
74
CB
Tmr
1-2
WDG
DMA
(8-chan.)
ROM
RTC (32KB)
C3
Gpio Flash
Serial
Sys
Ctr
Misc
Applic Subsys.
Basic Subsystem
Common Subsystems
A
Eth.
Mac
USB2.0
Dev
USB2.0
hub-
2host
HS Subsystem
SDRAM
Controller
-DDR2
-DDRmob
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5.1 Core architecture
The SoC internal architecture is based on several shared subsystem logic blocks
interconnected through a multilayer interconnection matrix as detailed in Figure 2.
The switch matrix structure allows different subsystem dataflows to be executed in parallel
improving the core platform efficiency.
High performance master agents are directly interconnected with the memory controller
reducing the memory access latency. Three different memory paths (two of them shared
with other masters) are reserved for the programmable logic to enhance the user application
throughput. The overall memory bandwidth assigned to each master port can be
programmed and optimized through an internal efficient weighted round-robin arbitration
mechanism.
The internal memory pool is completely configurable to improve the performance of the user
application custom logic.
11/66
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| PDF Descargar | [ Datasheet SPEAR-09-B042.PDF ] | |
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