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PDF SPEAR-09-P022 Data sheet ( Hoja de datos )

Número de pieza SPEAR-09-P022
Descripción Plus600 dual processor cores
Fabricantes STMicroelectronics 
Logotipo STMicroelectronics Logotipo



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No Preview Available ! SPEAR-09-P022 Hoja de datos, Descripción, Manual

SPEAR-09-P022
SPEAr™ Plus600 dual processor cores
Preliminary Data
Features
Dual ARM926EJ-S core @333 MHz
600 Kbyte reconfigurable logic array with 88
dedicated general purposes I/Os, 9 LVDS
channels and 128 Kbyte configurable internal
memory pool
Multilayer AMBA 2.0 compliant bus with fMAX
166 MHz
32 Kbyte ROM
8 Kbyte common static ram
Dynamic power saving features
High performance 8 channels DMA
Ethernet 10/100/1000 MAC with GMII/MII
Interface to external PHY
USB2.0 device with integrated PHY
2 USB2.0 host with integrated PHY
Ext. SDRAM memory interface:
– 8/16-bit (DDR1@200 MHz)
– 8/16-bit (DDR2@333 MHz)
Flashes interface:
– Nand 8/16-bit
www.DataSheet4US.ceomrial (up to 50 Mbps)
3-SPI master/slave up to 40 Mbps
I2C master/slave mode - high, fast and slow
speed
2 independent UART up to 460.8 Kbps with
software flow control mode.
IrDA (Fir-Mir-Sir) from 9.6 Kbps to 4 Mbps
speed-rate
Colour LCD controller:
– up to 1024x768 resolutions
– 24 bpp true colour TFT panel
PBGA420
– 16 bpp DSTN panel
10 GPIOs bidirectional signals with interrupt
capability
88 RAS-GPIOs user customizable bidirectional
signals (up to 4 clocks)
ADC 10-bit, 1MSPS, 8 analog inputs
JPEG codec accelerator
10 independent timers with programmable
prescaler
Real time clock
WatchDog
System controller
MISC internal control registers
JTAG (IEEE1149.1) interface
Description
SPEAr Plus600 is a powerful digital engine
belonging to SPEAr family, the innovative
customizable system-on-chip.
The device integrates two ARM 926 cores with a
large set of proven IPs and a big configurable
logic block that allow very fast customization of
unique and/or proprietary solution.
The SPEAR-09-P022 is designed for the -40 to
85 °C ambient temperature range..
Table 1. Device summary
Order code
SPEAR-09-P022
Package
PBGA420(23x23x1.81mm)
Packing
Tray
July 2008
Rev 3
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to
change without notice.
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SPEAR-09-P022 pdf
SPEAR-09-P022
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Main SPEAr Plus600 functional interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Crystal connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Crystal equivalent model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
RTC crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
RTC crystal equivalent model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
PBGA420 mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
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SPEAR-09-P022 arduino
SPEAR-09-P022
Pin description
Table 2. Pin description by functional group (continued)
Group
Signal name
Ball Direction
Function
Pin type
PL_GPIO_1
PL_GPIO_2
PL_GPIO_3
PL_GPIO_4
PL_GPIO_5
PL_GPIO_6
PL_GPIO_7
PL_GPIO_8
PL_GPIO_9
PL_GPIO_10
PL_GPIO_11
PL_GPIO_12
PL_GPIO_13
PL_GPIO_14
PL_GPIO_15
N4
N5
N6
M5
M4
M3
M2
M1
L1
L2
L3
L4
L5
K6
K5
PL_GPIO_16
PL_GPIO_17
PL PL_GPIO_18
PL_GPIO_19
PL_GPIO_20
PL_GPIO_21
K4
K3 TTL BIDIR buffer,
K2 I/O Programmable logic I/O 3.3 V capable, 4 mA
K1 3.3 V tolerant, PU
J1
J2
PL_GPIO_22
www.DataSheet4U.com PL_GPIO_23
PL_GPIO_24
PL_GPIO_25
PL_GPIO_26
PL_GPIO_27
J3
J4
J5
H5
H4
H3
PL_GPIO_28
PL_GPIO_29
PL_GPIO_30
PL_GPIO_31
PL_GPIO_32
PL_GPIO_33
H2
H1
G1
G2
G3
G4
PL_GPIO_34
PL_GPIO_35
G5
F5
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