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PDF HT82A620R Data sheet ( Hoja de datos )
| Número de pieza | HT82A620R | |
| Descripción | (HT82A520R / HT82A620R) Full Speed USB 8bit OTP MCU | |
| Fabricantes | Holtek Semiconductor | |
| Logotipo |  |
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HT82A520R/HT82A620R
Full Speed USB 8-Bit OTP MCU with SPI
Features
· Operating voltage:
fSYS = 6MHz: 2.2V~5.5V
fSYS = 12MHz: 4.0V~5.5V
· 4K´15 Program Memory
· 160´8 data memory RAM
· USB 2.0 Full Speed Compatible
· Single external interrupt input shared with I/O line
· Single 16-bit programmable Timer/Event Counters
with overflow interrupt
· Single SPI interfaces (master and slave mode)
shared with PA0~PA3
· Total of 4 Interrupts - INT, Timer, SPI, USB
· Watchdog Timer function
· Power down and wake-up functions to reduce power
consumption
· 16 channel 12-bit resolution A/D converter for
HT82A620R
· 3-channel 12-bit PWM output shared with three I/O
lines
· 24-Bidirectional I/O lines.
· Up to 0.33ms instruction cycle with 12MHz system
clock at VDD=5V
· Max. 4 endpoints supported - endpoint 0 included
· All endpoints support Interrupt, & bulk transfer
· Endpoint 0 supports control, interrupt and bulk
transfer
· All endpoints except endpoint 0 can be configured
as 8, 16, 32, 64 FIFO size
· Endpoint 0 has 8 byte FIFO
· Total FIFO size: 64+8 bytes (RAM0: 48 bytes;
RAM1:16 bytes, 8 bytes for endpoint0)
· 6-level subroutine nesting
· Bit manipulation instruction
· Table read instructions
· 63 powerful instructions
· All instructions executed in one or two instruction
cycles
· Low voltage reset function (2.0V±0.1%)
· 20/24/28-pin SSOP, 32-pin QFN package
· PB7 can configure as GPIO or VDDIO by option.
The power supply of the pin PB0~PB6 can be
optioned as VDD or VDDIO
General Description
The HT82A520R/HT82A620R are 8-bit high perfor-
mance RISC-like microcontrollers designed for USB
keyboard mouse and joystick product applications.
The advantages of low power consumption, I/O flexibil-
ity, programmable frequency divider, timer functions,
oscillator options, multi-channel A/D Converter, Pulse
Width Modulation function, Watchdog timer, SPI inter-
faces, Power Down and wake-up functions, enhance
the versatility of these devices to suit a wide range of ap-
plication possibilities such as sensor signal processing,
motor driving, industrial control, consumer products,
subsystem controllers, etc.
www.DataSheet4U.com
Selection Table
Part No.
HT82A520R
Data Program
Memory Memory
I/O
160´8 4K´15 24
HT82A620R
160´8
4K´15
24
Timer A/D PWM
16-bit´1 ¾ 12-bit´3
16-bit´1 12-bit´16 12-bit´3
SPI Package
1
20/24/28SSOP,
32QFN
1
20/24/28SSOP,
32QFN
Rev.1.00
1 October 23, 2009
1 page  
HT82A520R/HT82A620R
HT82A620R
Pin Name I/O
Options
Description
PA0/SCS
PA1/SCK
PA2/SDI
PA3/SDO
PA4/PWM0
PA5/PWM1
PA6/INT
PA7/TMR
Bi-directional 8-bit input/output port. Each bit can be configured as
wake-up input by option (bit option). Software instructions determine
I/O
Pull-high
Wake-up
NMOS or CMOS
if the pin is output or Schmitt Trigger input. When if output, Configura-
tion option may choose CMOS or NMOS. Configuration options de-
termine if the pins have pull-high resistors.
The TMR and INT are pin-shared with PA6 and PA7, respectively.
PA0~PA3 are shared with SPI function.
PA4~PA5 shared with PWM0~PWM1.
Bi-directional 8-bit input/output port. Software instructions determine
PB0/AN0/PWM2
PB1/AN1
PB2/AN2
PB3/AN3
PB4/AN4
PB5/AN5
PB6/AN6
PB7/AN7
I/O
Pull-high
Wake-up
PB7: I/O or VDDIO
PB0~PB6 power:
from VDD or
VDDIO
if the pin is a CMOS output or Schmitt Trigger input. Configuration op-
tions determine if the pins have pull-high resistors. PB is pin shared
with the A/D inputs. Once a PB line is selected as an A/D input, using
software control, the I/O function and pull-high resistor are disabled
automatically.
A configuration option determines whether PB7 is an I/O pin or a
power supply pin for PB0~PB6.
A configuration option determines whether the power supply for
PB0~PB6 is sourced from VDD or VDDIO
PB0 shared with PWM2.
PC0/AN8
PC1/AN9
PC2/AN10
PC3/AN11
PC4/AN12
PC5/AN13
PC6/AN14
PC7/AN15
Bi-directional 8-bit input/output port. Software instructions determine
if the pin is a CMOS output or Schmitt Trigger input. Configuration op-
I/O
Pull-high
Wake-up
tions determine if the pins have pull-high resistors. PC is pin shared
with the A/D inputs. Once a PB line is selected as an A/D input, using
software control, the I/O function and pull-high resistor are disabled
automatically
OSCI
OSCO
I
O
OSCI, OSCO are connected to an external 6MHz or 12MHz Crys-
¾ tal/resonator, determined by software instructions, for the internal
system clock
RESB
I ¾ Schmitt trigger reset input, active low
VDD
¾ ¾ Positive power supply
D -/Data
I/O
¾
USBD- line
The USB function is controlled by a software control register
www.DataSheet4U.Dco+m/CLK
I/O
¾
USBD+ line
The USB function is controlled by a software control register
V33O
O ¾ 3.3V regulator output
VSS
¾ ¾ Negative power supply, ground
Absolute Maximum Ratings
Supply Voltage ...........................VSS-0.3V to VSS+6.0V
Input Voltage..............................VSS-0.3V to VDD+0.3V
IOL Total ..............................................................150mA
Total Power Dissipation .....................................500mW
Storage Temperature ............................-50°C to 125°C
Operating Temperature.............................-0°C to 70°C
IOH Total............................................................-100mA
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed
in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
Rev.1.00
5 October 23, 2009
5 Page 
The following example shows how the table pointer and
table data is defined and retrieved from the
microcontroller. This example uses raw table data lo-
cated in the last page which is stored there using the
ORG statement. The value at this ORG statement is
²F00H² which refers to the start address of the last page
within the 4K Program Memory of device. The table
pointer is setup here to have an initial value of ²06H².
This will ensure that the first data read from the data ta-
ble will be at the Program Memory address ²F06H² or 6
locations after the start of the last page. Note that the
value for the table pointer is referenced to the first ad-
dress of the present page if the ²TABRDC [m]² instruc-
tion is being used. The high byte of the table data which
in this case is equal to zero will be transferred to the
TBLH register automatically when the ²TABRDL [m]² in-
struction is executed.
HT82A520R/HT82A620R
P ro g ra m C o u n te r
H ig h B y te
TB LP
P ro g ra m
M e m o ry
TB LH
T a b le C o n te n ts H ig h B y te
S p e c ifie d b y [m ]
T a b le C o n te n ts L o w B y te
T a b le R e a d - T B L P O n ly
TBH P
TB LP
P ro g ra m
M e m o ry
T B L H S p e c ifie d b y [m ]
H ig h B y te o f T a b le C o n te n ts L o w B y te o f T a b le C o n te n ts
T a b le R e a d - T B L P / T B H P
tempreg1 db
tempreg2 db
:
:
? ; temporary register #1
? ; temporary register #2
mov a,06h
; initialise table pointer - note that this address
; is referenced
mov tblp,a
:
:
; to the last page or present page
tabrdl
tempreg1 ; transfers value in table referenced by table pointer
; to tempregl
; data at prog. memory address ²F06H² transferred to
; tempreg1 and TBLH
dec tblp
; reduce value of table pointer by one
tabrdl
www.DataSheet4U.com
:
:
tempreg2
; transfers value in table referenced by table pointer
; to tempreg2
; data at prog.memory address ²F05H² transferred to
; tempreg2 and TBLH
; in this example the data ²1AH² is transferred to
; tempreg1 and data ²0FH² to register tempreg2
; the value ²00H² will be transferred to the high byte
; register TBLH
org F00h
; sets initial address of last page
dc 00Ah, 00Bh, 00Ch, 00Dh, 00Eh, 00Fh, 01Ah, 01Bh
:
:
Table Location Bits
Instruction
b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
TABRDC [m] PC11 PC10 PC9 PC8 @7 @6 @5 @4 @3 @2 @1 @0
TABRDL [m] 1 1 1 1 @7 @6 @5 @4 @3 @2 @1 @0
Table Location
Note: PC11~PC8: Current Program Counter bits
@7~@0: Table Pointer TBLP bits
TBHP register bit3~bit0 when TBHP is enabled
Rev.1.00
11 October 23, 2009
11 Page | ||
| Páginas | Total 70 Páginas | |
| PDF Descargar | [ Datasheet HT82A620R.PDF ] | |
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