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PDF AK4141 Data sheet ( Hoja de datos )
| Número de pieza | AK4141 | |
| Descripción | NICAM/A2/EIA-J Digital Stereo Decoder | |
| Fabricantes | Asahi Kasei Microsystems | |
| Logotipo |  |
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[AK4141]
= Preliminary =
AK4141
NICAM/A2/EIA-J Digital Stereo Decoder
GENERAL DESCRIPTION
The AK4141 is a NICAM/A2/EIA-J stereo decoder, which is optimized for Digital TV application. The
AK4141 achieves no alignment, few external components and high audio performance by digital stereo
decoding architecture. The AK4141 integrates a stereo sample rate converter (SRC) for asynchronous
digital audio sources such as HDMI, digital tuner, digital switches and sound processing functions such as
5-band equalizers. The AK4141 supports major audio data formats (MSB/LSB justified, I2S and TDM) to
interface with DSP, ADC, DAC. Therefore, the AK4141 is suitable for the AV systems such as Digital TV
and DVR.
FEATURES
1. Stereo Decoding
Capable of receiving Sound Intermediate Frequency (SIF) with Selector
and FM Demodulation
Automatic Gain Control (AGC: 100mVpp ~ 1Vpp) for SIF input
Alignment Free Digital Stereo Decoding
EIA-J
NICAM: B/G, L, I, D/K with FM/AM Mono
A2: B/G, D/K1, D/K2, D/K3, M/N
Automatic/Manual Stereo Decoding Standard Selection
Automatic/Manual Audio Mode (Stereo/MONO/two sounds) Selection
Signal Quality Detection for Auto Selection Mode
High FM Deviation Option (max: 540kHz)
I2S sampling rate (fs): 32k/44.1k/48kHz
2. Audio Processing (Two Stereos)
Automatic Level Control (ALC)
Balance
5-band Equalizer
Stereo Separation Emphasis
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Digital Volume Control with Soft Mute (+12dB~-115dB, 0.5dB/step)
Audio Data Interface:
I2S input x 5 (2 inputs: SRC available)
I2S output x 3
Master/Slave Mode
Audio Format: 24bit Left justified /Right justified / I2S or TDM
3. Asynchronous Sample Rate Converter (SRC)
Input Sample Rate: 8k~192kHz
fso/fsi: 1/6~6
4. Digital Audio Interface Transmitter (DIT) with Through Mode
5. Integrated X’tal Oscillator
6. Master Clock: 256fs/384fs/512fs/768fs/1024fs
7. I2C-bus Control Interface
8. Power Supply: 1.8V±0.1V, 3.3V±0.3V
9. Ta: -20 ~ 85°C
10. Package: 48pin LQFP
Rev. 0.3-PB
-1-
2008/01
1 page  
[AK4141]
PIN/FUNCTION
31 INT
O
Interrupt Pin
Outputs “L” when PDN Pin = “L”.
Decoder Standard Preference Control for 6.5MHz carrier.
32 A6M5
I
“L”: SECAM L NICAM
“H”: D/K1, D/K2, D/K3 or D/K NICAM
This Pin is internally ORed with A6M5 bit (default = “0”).
Master Mode Select Pin
33 MSN
I “L”: Slave mode if CKS[2:0] bits = “000”(default)
“H”: Master mode of MCLK = 256fs if CKS2 bit = “0”(default)
34 CAD0
I
Chip Address 0 pin
Should match CAD0 bit in I2C first byte.
35 CAD1
I
Chip Address 1 pin
Should match CAD1 bit in I2C first byte.
PLL Loop Filter 1 Pin
36 FILT1
O A 4.7nF capacitor should be connected to GND3 externally.
Hi-Z when PDN Pin = “L”.
ADC Voltage Reference High Pin
37 VREFH O A 0.1μF capacitor should be connected to GND3, and another 0.1μF capacitor
should be connected to VREFL Pin externally. Hi-Z when PDN Pin = “L”.
ADC Voltage Reference Low Pin
38 VREFL
O A 0.1μF capacitor should be connected to GND3 externally.
Hi-Z when PDN Pin = “L”.
39 GND3
- Ground Pin, 0V
40 SIF2
I Sound Intermediate Frequency(SIF) Input 2 Pin
ADC Common Voltage Output Pin.
41 VCOM
O A 1μF capacitor should be connected to GND3 externally. Hi-Z when PDN Pin =
“L”.
42 SIF1
I Sound Intermediate Frequency(SIF) Input 1 Pin
43 AVDD1 - Analog Power Supply Pin, 3.0V~3.6V
44 GND4
- Ground Pin, 0V
45 XTI
I X'tal Input Pin
46 XTO
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47 GND5
O
X'tal Output Pin.
Outputs “L” when PDN pin = “L”.
- Ground Pin, 0V
48 AVDD2 - Analog Power Supply Pin, 3.0V~3.6V
Note: All digital input pins should not be left floating.
Rev. 0.3-PB
-5-
2008/01
5 Page 
[AK4141]
SWITCHING CHARACTERISTICS (Continued)
(Ta=-20∼ 85°C; AVDD= 3.0~3.6V, DVDD=1.7~1.9V TVDD=1.7~3.6V; GND1=GND2=GND3=GND4=GND5=0V;
CL=20pF, Cb=400pF(SDA pin))
Parameter (Note 8)
Symbol
min
typ max Units
LRCK Timing (Slave Mode)
Normal mode (TDM=“0”)
LRCK Frequency
fs 32
48 kHz
Duty Cycle
TDM256 mode (TDM=“1”)
Duty
45
55 %
LRCK Frequency
fs 32
48 kHz
“H” time
tLRH
1/256fs
ns
“L” time
SRC Input
tLRL
1/256fs
ns
LRCK Frequency
fs 8
192 KHz
Duty Cycle
LRCK Timing (Master Mode)
Normal mode (TDM=“0”)
Duty
45
55 %
LRCK Frequency
fs 32
48 kHz
Duty Cycle
TDM256 mode (TDM=“1”)
Duty
50
%
LRCK Frequency
fs 32
48 kHz
“H” time
(Note 7)
tLRH
1/8fs
ns
Audio Interface Timing (Slave mode)
Normal mode (TDM=“0”)
SCLK Period
tBCK
160
ns
SCLK Pulse Width Low
tBCKL
65
ns
Pulse Width High
LRCK Edge to SCLK “↑”
(Note 9)
SCLK “↑” to LRCK Edge
(Note 9)
LRCK to SDTO(MSB) (Except I2S mode)
SCLK “↓” to SDTO
tBCKH
tLRB
tBLR
tLRS
tBSD
65
30
30
ns
ns
ns
35 ns
35 ns
SDTI Hold Time
tSDH
10
ns
SDTI Setup Time
TDM256 mode (TDM=“1”)
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tSDS
tBCK
10
81
ns
ns
SCLK Pulse Width Low
tBCKL
32
ns
Pulse Width High
LRCK Edge to SCLK “↑”
SCLK “↑” to LRCK Edge
SCLK “↓” to SDTO
(Note 9)
(Note 9)
tBCKH
tLRB
tBLR
tBSD
32
20
20
ns
ns
ns
20 ns
TDMIN Hold Time
tSDH
10
ns
TDMIN Setup Time
SRC Input (Note 10)
tSDS
10
ns
SCLK Period
tBCK
81
ns
SCLK Pulse Width Low
tBCKL
32
ns
Pulse Width High
LRCK Edge to SCLK “↑”
SCLK “↑” to LRCK Edge
(Note 9)
(Note 9)
tBCKH
tLRB
tBLR
32
20
20
ns
ns
ns
SDTI Hold Time
tSDH
10
ns
SDTI Setup Time
tSDS
10
ns
Rev. 0.3-PB
- 11 -
2008/01
11 Page | ||
| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet AK4141.PDF ] | |
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