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PDF AMIS-49587 Data sheet ( Hoja de datos )
| Número de pieza | AMIS-49587 | |
| Descripción | Power Line Carrier Modem | |
| Fabricantes | ON Semiconductor | |
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AMIS-49587
Power Line Carrier Modem
ON Semiconductor’s AMIS−49587 is an IEC 61334−5−1 compliant
power line carrier modem using spread−FSK (S−FSK) modulation for
robust low data rate communication over power lines. AMIS−49587 is
built around an ARM 7TDMI processor core, and includes the MAC
layer. With this robust modulation technique, signals on the power
lines can pass long distances. The half−duplex operation is
automatically synchronized to the mains, and can be up to
2400 bits/sec.
The product configuration is done via its serial interface, which
allows the user to concentrate on the development of the application.
The AMIS−49587 is implemented in ON Semiconductor mixed
signal technology, combining both analog circuitry and digital
functionality on the same IC.
Features
• Power Line Carrier Modem for 50 and 60 Hz Mains
• Fully compliant to IEC 61334−5−1 and CENELEC EN 50065−1
• Complete Handling of Protocol Layers Physical to MAC
• Programmable Carrier Frequencies from 9 to 95 kHz in 10 Hz Steps
• Half Duplex
• Data Rate Selectable: 300 – 600 – 1200 – 2400 baud (@ 50 Hz)
360 – 720 – 1440 – 2880 baud (@ 60 Hz)
• Synchronization on Mains
• Repetition Algorithm Boost the Robustness of Communication
• SCI Port to Application Microcontroller
• SCI Baudrate Selectable: 4.8 – 9.6 – 19.2 – 34.4 kb
• Power Supply 3.3 V
• Ambient Temperature Range: −40°C to +85°C
• These Devices are Pb−Free and are RoHS Compliant*
Typical Applications
• ARM: Automated Remote Meter Reading (Télérelevé)
• Remote Security Control
• Streetlight Control
• Transmission of Alerts (Fire, Gas Leak, Water Leak)
www.onsemi.com
281
PLCC 28 Lead
CASE 776AA
1 52
QFN52 8x8, 0.5P
CASE 485M
MARKING DIAGRAMS
ON ARM
XXXXYZZ
AMIS49587
C587-NAF e3
52
1 ON ARM
XXXXYZZ
AMIS49587
C587−NAF e3
XXXX = Date Code
Y = Plant Identifier
ZZ = Traceability Code
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 3 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2015
December, 2015 − Rev. 2
1
Publication Order Number:
AMIS−49587/D
1 page  
3.1 PLCC Packaging
AMIS−49587
3 PIN DESCRIPTION
M50Hz_IN 5
RX_DATA 6
TDO 7
TDI 8
TCK 9
TMS 10
TRSTB 11
4 3 2 1 28 27 26
AMIS−49587
25 TX _ENB
24 TEST
23 RESB
22 CRC
21 BR0
20 BR1
19 T_REQ
12 13 14 15 16 17 18
Figure 2. Pinout
Table 6. AMIS−49587 PLCC PIN FUNCTION DESCRIPTION
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Pin Name
VSSA
RX_OUT
RX_IN
REF_OUT
M50HZ_IN
RX_DATA
TDO
TDI
TCK
TMS
TRSTB
TX_DATA/
PRE_SLOT
XIN
XOUT
VSS
VDD
TXD
RXD
T_REQ
BR1
BR0
CRC
RESB
TEST
TX_ENB
TX_OUT
ALC_IN
VDDA
I/O
Out
In
Out
In
Out
Out
In
In
In
In
Out
In
Out
Out
In
In
In
In
Out
In
In
Out
Out
In
Type
P
A
A
A
A
D, 5V Safe
D
D
D
D
D
D, 5V Safe
A
A
P
P
D, 5V Safe
D, 5V Safe
D, 5V Safe
D, 5V Safe
D, 5V Safe
D, 5V Safe
D, 5V Safe
D
D, 5V Safe
A
A
P
Description
Analog ground
Output of receiver low noise operational amplifier
Positive input of receiver low noise operational amplifier
Reference output for stabilization
50/60 Hz input for mains zero cross detection
Data reception indication (open drain output)
Test data output
Test data input (internal pulldown)
Test clock (internal pulldown)
Test mode select (internal pulldown)
Test reset bar (internal pulldown, active low)
Data output corresponding to transmitted data or PRE_SLOT signal
(open drain output)
Xtal input (can be driven by an internal clock)
Xtal output (output floating when XIN driven by external clock)
Digital ground
3.3 V digital supply
SCI transmit output (open drain)
SCI receive input (Schmitt trigger input)
Transmit request input
SCI baud rate selection
SCI baud rate selection
Correct frame CRC indication (open drain output)
Master reset bar (Schmitt trigger input, active low)
Test enable (internal pulldown)
TX enable bar (open drain)
Transmitter output
Automatic level control input
3.3 V analog supply
P: Power pin
A: Analog pin
D: Digital pin
5V Safe: IO that support the presence of 5V on bus line
Out: Output signal
In: Input signal
In/Out: Bi−directional pin
www.onsemi.com
5
5 Page 
AMIS−49587
4 ELECTRICAL CHARACTERISTICS
4.1 DC AND AC CHARACTERISTICS
4.1.1 Oscillator: Pin XIN, XOUT
In production the actual oscillation of the oscillator and duty cycle will not be tested. The production test will be based on the
static parameters and the inversion from XIN to XOUT in order to guarantee the functionality of the oscillator.
Table 8. OSCILLATOR
Parameter
Test Conditions
Symbol
Min
Typ
Max Unit
Crystal frequency
(Note 1)
fCLK −100 ppm 24 +100 ppm MHz
Duty cycle with quartz connected
(Note 1)
40 61 %
Start−up time
Maximum Capacitive load on XOUT
Low input threshold voltage
High input threshold voltage
Low output voltage
(Note 1)
XIN used as clock input
XIN used as clock input
XIN used as clock input
XIN used as clock input,
XOUT = 2 mA
Tstartup
CLXOUT
VILXOUT
VIHXOUT
VOLXOUT
0.3 VDD
50
50
0.7 VDD
0.3
ms
pF
V
V
V
High input voltage
XIN used as clock input
VOHXOUT
1. Guaranteed by design. Maximum allowed series loss resistance up to 80 W.
VDD−0.3
V
4.1.2 Zero Crossing Detector and 50/60 Hz PLL: Pin M50HZ_IN
Table 9. ZERO CROSSING DETECTOR AND 50/60 Hz PLL
Parameter
Test Conditions
Symbol
Min
Typ
Max Unit
Maximum peak input current
Maximum average input current
Mains voltage (ms) range
During 1 ms
With protection resistor at
M50HZIN
ImpM50HZIN
ImavgM50HZIN
VMAINS
−20
−2
90
20 mA
2 mA
550 V
Rising threshold level
Falling threshold level
Hysteresis
Lock range for 50 Hz (Note 3)
Lock range for 60 Hz (Note 3)
Lock time (Note 3)
Lock time (Note 3)
Frequency variation without going out of
lock (Note 3)
(Note 2)
(Note 2)
(Note 2)
MAINS_FREQ = 0 (50 Hz)
MAINS_FREQ = 0 (60 Hz)
MAINS_FREQ = 0 (50 Hz)
MAINS_FREQ = 0 (60 Hz)
MAINS_FREQ = 0 (50 Hz)
VIRM50HZIN
VIFM50HZIN
VHY50HZIN
Flock50Hz
Flock60Hz
Tlock50Hz
Tlock60Hz
DF60Hz
0.82
0.4
45
54
1.9 V
V
V
55 Hz
66 Hz
15 s
20 s
0.1 Hz/s
Frequency variation without going out of
lock (Note 3)
MAINS_FREQ = 0 (60 Hz)
DF50Hz
0.1 Hz/s
Jitter of CHIP_CLK (Note 3)
JitterCHIP_CLK −25
25 ms
2. Measured relative to VSS.
3. These parameters will not be measured in production since the performance is totally dependent of a digital circuit which will be guaranteed
by the digital test patterns.
www.onsemi.com
11
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