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PDF AMIS-42700 Data sheet ( Hoja de datos )

Número de pieza AMIS-42700
Descripción Dual High Speed CAN Transceiver
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AMIS-42700
Dual High Speed CAN
Transceiver
General Description
Controller area network (CAN) is a serial communication protocol,
which supports distributed realtime control and multiplexing with
high safety level. Typical applications of CANbased networks can be
found in automotive and industrial environments.
The AMIS42700 DualCAN transceiver is the interface between
up to two physical bus lines and the protocol controller and will be
used for serial data interchange between different electronic units at
more than one bus line. It can be used for both 12 V and 24 V systems.
The circuit consists of following blocks:
Two differential line transmitters
Two differential line receivers
Interface to the CAN protocol handler
Interface to expand the number of CAN busses
Logic block including repeater function and the feedback suppression
Thermal shutdown circuit (TSD)
Short to battery treatment circuit
Due to the wide commonmode voltage range of the receiver inputs,
the AMIS42700 is able to reach outstanding levels of
electromagnetic susceptibility (EMS). Similarly, extremely low
electromagnetic emission (EME) is achieved by the excellent
matching of the output signals.
Key Features
Fully compatible with the ISO 118982 standard
www.DataSCheeertt4ifUie.cdom“Authentication on CAN Transceiver Conformance (d1.1)”
High speed (up to 1 Mbit/s in function of the bus topology)
Ideally suited for 12 V and 24 V industrial and automotive
applications
Low EME commonmodechoke is no longer required
Differential receiver with wide commonmode range (±35 V) for
high EMS
No disturbance of the bus lines with an unpowered node
Dominant timeout function
Thermal protection
Bus pins protected against transients in an automotive environment
Short circuit proof to supply voltage and ground
http://onsemi.com
PIN CONFIGURATION
NC 1
EN2 2
Text 3
Tx0 4
GND 5
GND 6
Rx0 7
Vref1 8
Rint 9
EN1 10
20 NC
19 CANH2
18 CANL2
17 GND
16 GND
15 GND
14 CANL1
13 CANH1
12 VCC
11 NC
SOIC 20
WC SUFFIX
CASE 751AQ
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 12 of this data sheet.
© Semiconductor Components Industries, LLC, 2009
January, 2009 Rev. 5
1
Publication Order Number:
AMIS42700/D

1 page




AMIS-42700 pdf
AMIS42700
Functional Description
Overall Functional Description
AMIS42700 is specially designed to provide the link
between the protocol IC (CAN controller) and two physical
bus lines. Data interchange between those two bus lines is
realized via the logic unit inside the chip. To provide an
independent switchoff of the transceiver units for both bus
systems by a third device (e.g. the mC), enableinputs for the
corresponding driving and receiving sections are provided.
As long as both lines are enabled, they appear as one logical
bus to all nodes connected to either of them.
The bus lines can have two logical states, dominant or
recessive. A bus is in the recessive state when the driving
sections of all transceivers connected to the bus are passive.
The differential voltage between the two wires is
approximately zero. If at least one driver is active, the bus
changes into the dominant state. This state is represented by
a differential voltage greater than a minimum threshold and
therefore by a current flow through the terminating resistors
of the bus line. The recessive state is overwritten by the
dominant state.
In case of a fault (like short circuit) is present on one of the
bus lines, it remains limited to that bus line where it occurs.
Data interchange from the protocol IC to the other bus
system and on this bus system itself can be continued.
AMIS42700 can be also used for only one bus system. If
the connections for the second bus system are simply left
open it serves as a single transceiver for an electronic unit.
For correct operation, it is necessary to terminate the open
bus by the proper termination resistor.
Logic Unit and CAN Controller Interface
The logic unit inside AMIS42700 provides data transfer
from/to the digital interface to/from the two busses and from
one bus to the other bus. The detailed function of the logic
unit is described in Table 3.
www.DataSAhelletd4iUg.ictaolminput pins, including ENBx, have an internal
pull-up resistor to ensure a recessive state when the input is
not connected or is accidentally interrupted. A dominant
state on the bus line is represented by a low-level at the
digital interface; a recessive state is represented by a
high-level.
Dominant state received on any bus (if enabled) causes a
dominant state on both busses, pin Rint and pin Rx0.
Dominant signal on any of the input pins Tx0 and Text
causes transmission of dominant on both bus lines (if
enabled).
Digital inputs Tx0 and Text are used for connecting the
internal logic’s of several IC’s to obtain versions with more
than two bus outputs (see Figure 4: Application Diagram
CAN-bus Extender). They have also a direct logical link to
pins Rx0 and Rint independently on the EN1x pins
dominant on Tx0 is directly transferred to both Rx0 and Rint
pins, dominant on Text is only transferred to Rx0.
Transmitters
The transceiver includes two transmitters, one for each
bus line, and a driver control circuit. Each transmitter is
implemented as a push and a pull driver. The drivers will be
active if the transmission of a dominant bit is required.
During the transmission of a recessive bit all drivers are
passive. The transmitters have a builtin current limiting
circuit that protects the driver stages from damage caused by
accidental short circuit to either positive supply voltage or
to ground. Additionally a thermal protection circuit is
integrated.
The driver control circuit ensures that the drivers are
switched on and off with a controlled slope to limit EME.
The driver control circuit will be controlled itself by the
thermal protection circuit, the timer circuit and the logic
unit.
The enable signal ENBx allows the transmitter to be
switched off by a third device (e.g. the mC). In the disabled
state (ENBx = high) the corresponding transmitter behaves
as in the recessive state.
Table 3. Function of the Logic Unit (bold letters describe input signals)
EN1B
EN2B
TX0
TEXT
Bus 1 State
0 0 0 0 dominant
0 0 0 1 dominant
0 0 1 0 dominant
0 0 1 1 recessive
0 0 1 1 dominant (Note 3)
0 0 1 1 dominant
01 0 0
01 0 1
01 1 0
01 1 1
01 1 1
3. Dominant detected by the corresponding receiver.
dominant
dominant
dominant
recessive
dominant (Note 3)
Bus 2 State
dominant
dominant
dominant
recessive
dominant
dominant (Note 3)
recessive
recessive
recessive
recessive
recessive
RX0
0
0
0
1
0
0
0
0
0
1
0
RINT
0
0
1
1
0
0
0
0
1
1
0
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AMIS-42700 arduino
Tx0/
Text
CANHx
AMIS42700
+5V
100 nF
VCC
12
Text 3
Vref
8 13 CANH1
Rint
Tx0
9
14 CANL1
AMIS42700 19 CANH2
4
Rx0
7
10
2
17 16 15 6 518 CANL2
EN1 EN2
GND
RLT
60 W
RLT
60 W
Figure 7. Test Circuit for Timing Characteristics
CLT
100 pF
CLT
100 pF
HIGH
LOW
CANLx
Vi(dif) =
VCANH VCANL
0,9V
Rx0/
Rint
td(TxRx)
www.DataShtde(Text4BUUS.ocno) m
0,3 x VCC
0,5V
0,9V
0,7 x VCC
0,3 x VCC
td(TxRx)
td(TxBUSoff)
td(BUSonRx)
Figure 8. Timing Diagram for AC Characteristics
0,5V
dominant
recessive
0,7 x VCC
td(BUSoffRx)
http://onsemi.com
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