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PDF AMIS-42665 Data sheet ( Hoja de datos )
| Número de pieza | AMIS-42665 | |
| Descripción | High-Speed Low Power CAN Transceiver | |
| Fabricantes | ON Semiconductor | |
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AMIS-42665
High-Speed Low Power
CAN Transceiver
Description
The AMIS−42665 CAN transceiver is the interface between a
controller area network (CAN) protocol controller and the physical
bus and may be used in both 12 V and 24 V systems. The transceiver
provides differential transmit capability to the bus and differential
receive capability to the CAN controller.
Due to the wide common−mode voltage range of the receiver inputs,
the AMIS−42665 is able to reach outstanding levels of
electromagnetic susceptibility (EMS). Similarly, extremely low
electromagnetic emission (EME) is achieved by the excellent
matching of the output signals.
The AMIS−42665 is a new addition to the CAN high−speed
transceiver family and offers the following additional features:
Features
• Wake−up (WU) Over Bus
• Voltage Source via VSPLIT Pin for Stabilizing the Recessive Bus
Level (Further EMC Improvement)
• Ideal Passive Behavior when Supply Voltage is Removed
• Extremely Low Current Standby Mode
• Compatible with the ISO 11898 Standard (ISO 11898−2, ISO
11898−5 and SAE J2284)
• High Speed (up to 1 Mbps)
• Ideally Suited for 12 V and 24 V Industrial and Automotive
Applications
• Extremely Low Current Standby Mode with Wake−up via the Bus
www.Dat•aSLheoewt4UE.McoEmCommon−Mode Choke is No Longer Required
• Differential Receiver with Wide Common−Mode Range ($35 V) for
High EMS
• Transmit Data (TxD) Dominant Time−out Function
• Thermal Protection
• Bus Pins Protected against Transients in an Automotive Environment
• Power Down Mode in which the Transmitter is Disabled
• Bus and VSPLIT Pins Short Circuit Proof to Supply Voltage and
Ground
• Logic Level Inputs Compatible with 3.3 V Devices
• These are Pb−Free Devices
http://onsemi.com
MARKING
DIAGRAM
8
1
SOIC−8
CASE 751
8
XXXXX
ALYW
G
1
XXXXX = Specific Device Code
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
PIN ASSIGNMENT
TxD 1
GND 2
VCC 3
RxD 4
8 STB
7 CANH
6 CANL
5 VSPLIT
(Top View) PC20040829.1
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
© Semiconductor Components Industries, LLC, 2009
January, 2009 − Rev. 7
1
Publication Order Number:
AMIS−42665/D
1 page  
AMIS−42665
detected by the low−power differential receiver, the signal
is first filtered and then verified as a valid wake signal after
a time period of tdbus, the RxD pin is driven low by the
transceiver to inform the controller of the wake−up request.
Split Circuit
The VSPLIT Pin is operational only in normal mode. In
standby mode this pin is floating. The VSPLIT is connected
as shown in Figure 2 and its purpose is to provide a stabilized
DC voltage of 0.5 x VCC to the bus avoiding possible steps
in the common−mode signal therefore reducing EME. These
unwanted steps could be caused by an unpowered node on
the network with excessive leakage current from the bus that
shifts the recessive voltage from its nominal 0.5 x VCC
voltage.
Wake−up
When a valid wake−up (dominant state longer than tdbus)
is received during the standby mode the RxD pin is driven
low. Wake−up behavior in case of a permanent dominant –
due to, for example, a bus short – represents the only
difference between the circuit sub−versions listed in the
Ordering Information table. It is depicted in Figures 3 and 4.
When the standby mode is entered while a dominant is
present on the bus, the “unconditioned bus wake−up”
versions will signal a bus−wakeup immediately after the
state transition (seen as a High−level glitch on RxD). The
other version (differing purely by a metal−level
modification in the digital part) will signal bus−wakeup only
after the initial dominant is released. In this way it’s ensured,
that a CAN bus can be put to a low−power mode even if the
nodes have a level sensitivity to RxD pin and a permanent
dominant is present on the bus.
www.DataSheet4U.com
CANH
CANL
Overtemperature Detection
A thermal protection circuit protects the IC from damage
by switching off the transmitter if the junction temperature
exceeds a value of approximately 160°C. Because the
transmitter dissipates most of the power, the power
dissipation and temperature of the IC is reduced. All other
IC functions continue to operate. The transmitter off−state
resets when Pin TxD goes high. The thermal protection
circuit is particularly needed when a bus line short circuits.
TxD Dominant Time−out Function
A TxD dominant time−out timer circuit prevents the bus
lines being driven to a permanent dominant state (blocking
all network communication) if Pin TxD is forced
permanently low by a hardware and/or software application
failure. The timer is triggered by a negative edge on pin TxD.
If the duration of the low−level on Pin TxD exceeds the
internal timer value tdom(TxD), the transmitter is disabled,
driving the bus into a recessive state. The timer is reset by a
positive edge on Pin TxD. See Figure 10.
This TxD dominant time−out time (tdom(TxD)) defines the
minimum possible bit rate to 40 kbps.
Fail Safe Features
A current−limiting circuit protects the transmitter output
stage from damage caused by accidental short circuit to
either positive or negative supply voltage, although power
dissipation increases during this fault condition.
The pins CANH and CANL are protected from
automotive electrical transients (according to ISO 7637; see
Figure 5). Pins TxD and STB are pulled high internally
should the input become disconnected. Pins TxD, STB and
RxD will be floating, preventing reverse supply should the
VCC supply be removed.
tdbus
tdbus
STB
RxD
unconditioned WU
Normal
Standby*
time
*Even if bus dominant signals longer than tdbus are echoed on RxD, the transceiver
stays in standby mode until STB is released.
Figure 3. AMIS42665TJAA1/3 Wake−up Behavior
tdbus
CANH
CANL
STB
RxD
Normal
Standby*
time
*On this derivative, bus dominant signals longer than tdbus are echoed on RxD after the bus passed through
a recessive time following the trigtger of STB. The transceiver stays in standby mode until STB is released.
Figure 4. AMIS42665TJAA6 Wake−up Behavior
http://onsemi.com
5
5 Page 
AMIS−42665
PACKAGE DIMENSIONS
−X−
A
SOIC−8
CASE 751−07
ISSUE AJ
B
−Y−
−Z−
H
85
S 0.25 (0.010) M Y M
1
4
K
G
D
C
SEATING
PLANE
N X 45 _
0.10 (0.004)
M
J
0.25 (0.010) M Z Y S X S
SOLDERING FOOTPRINT*
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
MILLIMETERS
INCHES
DIM MIN MAX MIN MAX
A 4.80 5.00 0.189 0.197
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.053 0.069
D 0.33 0.51 0.013 0.020
G 1.27 BSC 0.050 BSC
H 0.10 0.25 0.004 0.010
J 0.19 0.25 0.007 0.010
K 0.40 1.27 0.016 0.050
M 0_ 8_ 0_ 8_
N 0.25 0.50 0.010 0.020
S 5.80 6.20 0.228 0.244
1.52
0.060
7.0
0.275
4.0
0.155
www.DataSheet4U.com
0.6
0.024
1.270
0.050
ǒ ǓSCALE 6:1
mm
inches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: [email protected]
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5773−3850
http://onsemi.com
11
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
AMIS−42665/D
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