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PDF AMIS-30585 Data sheet ( Hoja de datos )
| Número de pieza | AMIS-30585 | |
| Descripción | S-FSK PLC Modem | |
| Fabricantes | ON Semiconductor | |
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AMIS-30585
S-FSK PLC Modem
General Description
The AMIS−30585 is a half duplex S−FSK modem and is dedicated
for the data transmission on low− or medium−voltage power lines.
The device offers complete handling of the protocol layers from the
physical up to the MAC. AMIS−30585 complies with the EN 50065
CENELEC, IEC 1334−4−32 and the IEC 1334−5−1 standards.
It operates from a single 3.3 V power supply and is interfaced to the
power line by an external power driver and transformer. An internal
PLL is locked to the mains frequency (50 Hz or 60 Hz) and is used to
synchronize the data transmission at data rates of 300, 600 and 1200
baud for a 50 Hz mains frequency, corresponding to 3.6 or 12 data bits
per half cycle of the mains frequency (50 Hz or 60 Hz).
Features
• Complies with IEC 1334−5−1 and IEC 1334−4−32
• Suited for 50 Hz or 60 Hz Mains
• Complete Modem for Data Communication on Power Line
• S−FSK Modulation
• Programmable Carrier in the Range of 9 kHz to 95 kHz
• Half Duplex up to 1440 bit/s
• Supports Chorus Transmission
• Programmable Configuration
• Internal ARM Microprocessor
• Serial Communication Interface (SCI) Port
• Low Power, 3 V Operation
• This is a Pb−Free Device*
www.DatAaSphpeleict4aUti.oconms
• IEC1334Utility PLC Modem
• Remote Meter Reading
• Utility Load Controls
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
http://onsemi.com
1
PLCC 28
A SUFFIX
CASE 776AA
MARKING DIAGRAM
AMIS30585AGA = Specific Device Code
XXXX = Date Code
Y = Plant Identifier
ZZ = Traceability Code
G = Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
© Semiconductor Components Industries, LLC, 2008
December, 2008 − Rev. 2
1
Publication Order Number:
AMIS−30585/D
1 page  
AMIS−30585
transmission request. So this pin is used as an input pin for
the chip in the normal working mode. This signal is used in
order to initiate a local communication from the
microcontroller to the AMIS−30585. The T_REQ signal is
active when low. IO0 and IO1 are assigned to drive external
LED. The embedded software defines pin activation.
Figure 3. External Component Connection
The goal of the CDREF capacitance is to put the DC
voltage of the received signal at the right level for the
internal components. See also description of the pin
REF_OUT.
Table 2. VALUE OF THE RESISTORS AND
CAPACITORS
C1 560 pF
C2 560 pF
R1 82 KW
R2 39 KW
CDREF
1 mF
Pin 4: REF_OUT
REF_OUT is the analog output pin, which provides the
voltage reference used by the A/D converter. This pin must
be decoupled from the analog ground by a 1 mF ±10 percent
ceramic capacitance (CDREF). This must be done as close
as possible on the PCB. See Figure 4. It is not allowed to load
this pin with other impedance load.
Pin 5: M50HZ_IN
M50HZ_IN is the mains frequency analog input pin − 50
or 60 Hz. This pin is used to detect the crossing of the zero
www.DatvaoSlhteaegte4Uon.coomne selected phase. This information is used, after
filtering with the internal PLL, to synchronize frames with
the mains frequency. In case of direct connection to the
mains, the use of a series resistor of 1 MW is advised in order
to limit the current flowing through the protection diodes.
Pin 6, 19 and 22: IO0, IO1 and IO2
IO0, IO1 and IO2 are general−purpose digital input and
output pins. Only the IO2 pin is used – this is an input for the
chip. All IOs support 5 V level on the bus (5 V safe IO).
When used as outputs, they must be able to deliver the 5 V
on the bus if necessary. Outputs are open drain NMOS. The
high level is created by opening the internal open drain
MOS. The 5 V level is obtained by the use of an external
pull−up resistance. Figure 4 gives a representation of a 5 V
safe IO. A typical value for the pull−up resistance “RES” is
10 KW. With a larger value for “RES”, the current flowing
through this resistance is reduced, hence the switch time
from 0 V up to 5 V. IO2 pin is used as T_REQ signal, i.e. the
Figure 4. Representation of 5V Safe I/O
Pin 7, 8, 9, 10, and 11: TDO, TDI, TCK, TMS, and
TRSTB
All these pins are part of the JTAG bus interface. It will be
connected to the ARM ICE interface box. This provides an
access to the embedded ARM processor. These pins are used
during the debugging of the embedded software. Pin
characteristics are in−line with the ARM JTAG interface
specification. They will not be described here. Input pins
(TDI, TCK, TMS, and TRSTB) contain internal pull−down
resistance. TDO is an output. When not in use, the JTAG
interface pins may be left floating.
Pin 12: TX_DATA
TX_DATA provides the digital output signal not
modulated. It gives the logical level associated with the
transmitted frequency. So, to transmit a frequency fs, the
TX_DATA logical state is 0 and is present on TX_DATA. To
transmit a frequency fm, the TX_DATA logical state is 1.
This output pin is an open drain. An external pull−up
resistance is needed to perform the voltage level associated
with a logical one (as for the IOx pins).
Pin 13: XIN
XIN is the analog input pin of the oscillator. It is connected
to the interval oscillator inverter gain stage. The clock signal
can be created either internally with the external crystal and
two capacitors or by connecting an external clock signal to
XIN. For the internal generation case, the two external
capacitors and crystal are placed as shown in Figure 5. For
the external clock connection, the signal is connected to XIN
and XOUT is left unused.
http://onsemi.com
5
5 Page 
AMIS−30585
Oscillator: Pin XIN, XOUT
In production the actual oscillation of the oscillator and duty cycle will not be tested. The production test will be based on
the static parameters and the inversion from XIN to XOUT in order to guarantee the functionality of the oscillator.
Table 8. OSCILLATOR
Parameter
Description
Condition
Min.
Max.
Unit
fCLK Crystal frequency
(Note 8)
24 MHz
−100 ppm
24 MHz
+100 ppm
Duty cycle with quartz connected
(Note 8)
30 70 %
Tstartup
Start−up time
(Note 8)
50 Ms
CLXOUT
Maximum Capacitive load on XOUT XIN used as clock input
50 pF
VILXOUT
Low input threshold voltage
XIN used as clock input
−0.3 VDD
V
VIHXOUT
High input threshold voltage
XIN used as clock input
0.7 vdd
V
VOLXOUT Low output voltage
XIN used as clock input, XOUT = 2 mA
0.3 V
VOHXOUT High input voltage
XIN used as clock input
VDD−0.3
V
8. For the design of the oscillator crystal parameters have been taken from the data sheet [8]. The series loss resistance for this type of crystal
is maximum 50 W. However the oscillator cell has been designed with some margin for series loss resistance up to 80 W.
Table 9. ZERO CROSSING DETECTOR AND 50/60HZ PLL: Pin M50HZ_IN
Parameter
Description
Condition
Min.
Max.
Unit
Imaxp
M50HZIN
Maximum peak input current
−20 20 mA
Imaxavg
M50HZIN
Maximum average input current
during 1 ms
−2 2 mA
VMAINS
VIRM50HZIN
VIFM50HZIN
VHY50HZIN
Flock50Hz
Flock60Hz
Tlock50Hz
www.DataShTeleotc4kU60.cHozm
DF60Hz
Mains voltage (ms) range
Rising threshold level
Falling threshold level
Hysteresis
Lock range for 50 Hz (Note 10)
Lock range for 60 Hz (Note 10)
Lock time (Note 10)
Lock time (Note 10)
Frequency variation without going
out of lock (Note 10)
With protection resistor at M50HZIN
(Note 9)
(Note 9)
(Note 9)
MAINS_FREQ = 0 (50 Hz)
MAINS_FREQ = 0 (60 Hz)
MAINS_FREQ = 0 (50 Hz)
MAINS_FREQ = 0 (60 Hz)
MAINS_FREQ = 0 (50 Hz)
90
0.9
0.4
45
54
550 V
1.9 V
V
V
55 Hz
66 Hz
10 S
10 S
0.1 Hz/s
DF50Hz
Frequency variation without going
out of lock (Note 10)
MAINS_FREQ = 0 (60 Hz)
0.1 Hz/s
JitterCHIP_CLK Jitter of CHIP_CLK (Note 10)
−60 60 ms
9. Measured relative to VSS.
10. These parameters will not be measured in production since the performance is totally dependent of a digital circuit which will be guaranteed
by the digital test patterns.
http://onsemi.com
11
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| PDF Descargar | [ Datasheet AMIS-30585.PDF ] | |
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