PDF CY28551 Data sheet ( Hoja de datos )

Número de pieza	CY28551
Descripción	Universal Clock Generator
Fabricantes	Cypress Semiconductor
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CY28551 Universal Clock Generator for Intel, VIA, and SIS® Features • Compliant to Intel® CK505 • Selectable CPU clock buffer type for Intel P4 or K8 selection • Selectable CPU frequencies • Universal clock to support Intel, SiS and VIA platform • 0.7V Differential CPU clock for Intel CPU • 3.3V Differential CPU clock for AMD K8 • 100 MHz differential SRC clocks • 96 MHz differential dot clock • 133 MHz Link clock • 48 MHz USB clock • 33 MHz PCI clocks • Dynamic Frequency Control • Dial-A-Frequency® • WatchDog Timer • Two Independent Overclocking PLLs • Low-voltage frequency select input • I2C support with readback capabilities • Ideal Lexmark Spread Spectrum profile for maximum electromagnetic interference (EMI) reduction • 3.3V Power supply • 64-pin QFN package CPU SRC SATA PCI REF LINK DOT96 24_48M 48M x 2 x 8 x1 x 7 x 3 x2 x1 x1 x 1 Block Diagram Xin 14.318MHz Xout Crystal PLLReference DOC[2:1] FS[D:A] SEL_P4_K8 PLL1 Divider CPU www.DataSheet4U.com SEL[1:0] PLL2 Divider PCIEX Multiplexer Controller PLL3 Divider SATA TPWR_GD#/PD SEL24_48 RESET_I# SDATA SCLK PLL4 Fixed Divider I2C Logic WDT Pin Configuration VDD_REF REF[2:0] VDD_CPU CPUT[1:0] CPUC[1:0] VDD_PCIEX PCIET[8:1] PCIEC[8:1] VDD_SATA PCIET0 /SATAT PCIEC0/SATAC VDD_DOT DOT96T/SATAT/LINK0 DOT96C/SATAC/LINK1 VDD_PCI PCI[6:0] 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 PCI6_F 1 48 VDDREF VDD48 2 SEL24_48 / 24_48M 3 47 SCLK 46 SDATA SEL1/48M 4 45 VTTPWRG#/PD VSS48 5 44 CPUT0 VDDDOT 6 43 CPUC0 LINK0/DOT96T/SATAT 7 42 VDDCPU LINK1/DOT96C/SATAC 8 VSSDOT 9 CY28551 41 CPUT1 40 CPUC1 VDDSATA 10 39 VSSCPU SATAT/PCIEXT0 11 38 *DOC2 SATAC/PCIEXC0 12 37 VSSA VSSSATA 13 36 VDDA PCIEXT1 14 35 PCIEXT8/CPU_STP# PCIEXC1 15 34 PCIEXC8/PCI_STP# VSSPCIE 16 33 VDDPCIE 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 VDD_48 48M 24_48M SRESET# Indicates internal pull up ** indicates internal pull down Cypress Semiconductor Corporation Document #: 001-05675 Rev. C • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised July 26, 2006 1 page Table 3. Block Read and Block Write Protocol Bit 1 8:2 9 10 18:11 19 27:20 28 36:29 37 45:38 46 .... .... .... .... Block Write Protocol Description Start Slave address – 7 bits Write Acknowledge from slave Command Code – 8 bits Acknowledge from slave Byte Count – 8 bits (Skip this step if I2C_EN bit set) Acknowledge from slave Data byte 1 – 8 bits Acknowledge from slave Data byte 2 – 8 bits Acknowledge from slave Data Byte/Slave Acknowledges Data Byte N – 8 bits Acknowledge from slave Stop Table 4. Byte Read and Byte Write Protocol Byte Write Protocol www.DataShBeeitt4U.com 1 Start Description 8:2 Slave address – 7 bits 9 Write 10 Acknowledge from slave 18:11 Command Code – 8 bits 19 Acknowledge from slave 27:20 Data byte – 8 bits 28 Acknowledge from slave 29 Stop CY28551 Bit 1 8:2 9 10 18:11 19 20 Block Read Protocol Description Start Slave address – 7 bits Write Acknowledge from slave Command Code – 8 bits Acknowledge from slave Repeat start 27:21 28 29 37:30 38 46:39 47 55:48 56 .... .... .... .... Slave address – 7 bits Read = 1 Acknowledge from slave Byte Count from slave – 8 bits Acknowledge Data byte 1 from slave – 8 bits Acknowledge Data byte 2 from slave – 8 bits Acknowledge Data bytes from slave/Acknowledge Data Byte N from slave – 8 bits NOT Acknowledge Stop Bit 1 8:2 9 10 18:11 19 20 27:21 28 29 37:30 38 39 Byte Read Protocol Description Start Slave address – 7 bits Write Acknowledge from slave Command Code – 8 bits Acknowledge from slave Repeated start Slave address – 7 bits Read Acknowledge from slave Data from slave – 8 bits NOT Acknowledge Stop Document #: 001-05675 Rev. C Page 5 of 30 5 Page CY28551 Byte 13: Control Register 13 Bit @Pup 51 Type R/W Name Time_Scale 40 R/W WD_Alarm 3 0 R/W WD_TIMER2 2 0 R/W WD_TIMER1 1 0 R/W WD_TIMER0 00 R/W WD_EN Description Time_Scale allows selection of WD time scale 0 = 294 ms, 1 = 2.34 s WD_Alarm is set to ‘1’ when the watchdog times out. It is reset to ‘0’ when the system clears the WD_TIMER time stamp Watchdog timer time stamp selection 000: Reserved (test mode) 001: 1 * Time_Scale 010: 2 * Time_Scale 011: 3 * Time_Scale 100: 4 * Time_Scale 101: 5 * Time_Scale 110: 6 * Time_Scale 111: 7 * Time_Scale Watchdog timer enable. When the bit is asserted, Watchdog timer is triggered and time stamp of WD_Timer is loaded 0 = Disable, 1 = Enable Byte 14: Control Register 14 Bit @Pup 70 60 Type R/W R/W 50 40 30 20 10 00 R/W R/W R/W R/W R/W R/W www.DataSheet4U.com Byte 15: Control Register 15 Bit @Pup 70 60 50 40 30 20 10 00 Type R/W R/W R/W R/W R/W R/W R/W R/W Name CPU_DAF_N7 CPU_DAF_N6 CPU_DAF_N5 CPU_DAF_N4 CPU_DAF_N3 CPU_DAF_N2 CPU_DAF_N1 CPU_DAF_N0 Name CPU_DAF_N8 CPU_DAF_M6 CPU_DAF_M5 CPU_DAF_M4 CPU_DAF_M3 CPU_DAF_M2 CPU_DAF_M1 CPU_DAF_M0 Description If Prog_CPU_EN is set, the values programmed in CPU_DAF_N[8:0] and CPU_DAF_M[6:0] will be used to determine the CPU output frequency. The setting of the FS_Override bit determines the frequency ratio for CPU and other output clocks. When it is cleared, the same frequency ratio stated in the Latched FS[E:A] register will be used. When it is set, the frequency ratio stated in the FSEL[3:0] register will be used Description If Prog_CPU_EN is set, the values programmed in CPU_DAF_N[8:0] and CPU_DAF_M[6:0] will be used to determine the CPU output frequency. The setting of the FS_Override bit determines the frequency ratio for CPU and other output clocks. When it is cleared, the same frequency ratio stated in the Latched FS[E:A] register will be used. When it is set, the frequency ratio stated in the FSEL[3:0] register will be used. Document #: 001-05675 Rev. *C Page 11 of 30 11 Page

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