PDF CY28510 Data sheet ( Hoja de datos )

Número de pieza	CY28510
Descripción	Peripheral I/O Clock Generator
Fabricantes	Cypress Semiconductor
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No Preview Available ! 510 CY28510 Features • 15 33.27-MHz or 66.669-MHz clock outputs • 1 REF 14.318 MHz • Divide by 2, spread spectrum and output enable all se- lectable on a per-output basis via I2C register bits • Divide by 2 mode default values strappable on a per-group basis • Output Enable pin controls all outputs Block Diagram Peripheral I/O Clock Generator • I2C Compatible Programmability With Block and Byte Modes • I2C Operates Up to 1MHz • I2C Address Selection of D0, D2, D4 or D6 • 48 Pin SSOP Package Pin Configuration XIN REF PLL 1with Spread Spectrum 66MHz CLK_STOP# PLL 2 no Spread Spectrum 66MHz (Group Frequency Select, 33 or 66MHz) GFS0 SCLK SDATA I2C ADDSEL(0:1) www.DataSheet4U.com GFS1 GFS2 GFS3 Mux ÷2 Mux ÷2 Mux ÷2 Mux ÷2 Mux ÷2 Mux ÷2 Mux ÷2 Mux ÷2 Mux ÷2 Mux ÷2 Mux ÷2 Mux ÷2 Mux ÷2 Mux ÷2 Mux ÷2 CLKG0_0 CLKG0_1 CLKG0_2 CLKG0_3 CLKG0_4 CLKG0_5 CLKG0_6 CLKG0_7 CLKG1_0 CLKG1_1 CLKG1_2 CLKG1_3 CLKG2_0 CLKG2_1 CLKG3 GFS3 REF GFS0 VDDX VSSX XIN XOUT VDDC ADDSEL0 ADDSEL1 VSSC CLK_STOP# SCLK SDATA GFS1 GFS2 OE CLKG3 VDDQ3 VSSQ3 VSSQ2 CLKG2_1 CLKG2_0 VDDQ2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 VDDQ0 47 CLKG0_0 46 CLKG0_1 45 VSSQ0 44 CLKG0_2 43 VDDQ0 42 VSSQ0 41 CLKG0_3 40 CLKG0_4 39 VDDQ0 38 CLKG0_5 37 CLKG0_6 36 CLKG0_7 35 VSSQ0 34 VDDQ1 33 CLKG1_0 32 CLKG1_1 31 VSSQ1 30 VDDQ1 29 CLKG1_2 28 CLKG1_3 27 VSSQ1 26 VDDA 25 VSSA OE Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Document #: 38-07542 Rev. Revised April 28, 2003 1 page CY28510 Byte 1: Clock Enable Register 2 Bit @Pup Name 71 CLKG1_0 1 = enabled, 0 = tri-state 61 CLKG1_1 1 = enabled, 0 = tri-state 51 CLKG1_2 1 = enabled, 0 = tri-state 41 CLKG1_3 1 = enabled, 0 = tri-state 31 CLKG2_0 1 = enabled, 0 = tri-state 21 CLKG2_1 1 = enabled, 0 = tri-state 11 CLKG3 1 = enabled, 0 = tri-state 01 REF 1 = enabled, 0 = tri-state Byte 2: Clock Spread Spectrum Control Register Description Bit @Pup 70 60 50 40 30 21 10 00 Name CPNTRL1 SWFSEL MSTRSRD SST1 SST0 Description B2b7, B2b6: 00 = normal, 01 = testb_output, 10 = PD_resetb, 11 = normal Charge Pump Control Bit1. See Table 4. Refer to CPNTRL0 in Byte 4, bit 0. CLK output strength, 0 = low, 1 = high. 0=GFS(3:0) controls output frequency. 1 =I 2C selection of output frequency. Output frequencies should be set in Clock Frequency Select Registers before enabling them. Master Spread Spectrum Enable. 1 = enabled, 0 = disabled. SST1 Select spread percentage. See Table 5 SST0 Select spread percentage. See Table 5 Table 4. Charge Pump Control [1] SST1 SST0 00 www.DataSh0eet4U.com 1 10 11 % Spread 100% 114% 143% 88% PLL Bandwidth 18 to 20 KHz 21 to 23 KHz 24 to 26 KHz 15 to 17 KHz Notes: 1. The bandwidth of the non-spread PLL is 80 KHz. 2. Glitch free operation for both enabling and disabling Spread Spectrum Table 5. Spread Spectrum Table [2] SST1 0 0 1 1 SST0 0 1 0 1 % Spread –0.25% Down spread Lexmark profile –0.50% Down spread Lexmark profile –1.0% Down spread Lexmark profile –1.0% Down spread Linear profile Document #: 38-07542 Rev. Page 5 of 13 5 Page CY28510 AC Electrical Specifications Parameter Description Condition CLK FVCO TDC TRISE/TFALL TGSKEW1 VCO Frequency Range Measured at 1.5V CLK Duty Cycle Measured at 1.5V CLK Rise and Fall Times Measured from 0.4V to 2.4V Any CLK to Any CLK Clock Skew Measured at 1.5V, with Spread within a Group Spectrum disabled. TGSKEW2 Any CLK to Any CLK Clock Skew Measured at 1.5V, with Spread within any Group Spectrum disabled. TCCJ1 CLK Cycle-to-Cycle Jitter Measured at 1.5V and all CLKs running the same frequency with Spread Spectrum disabled. TCCJ2 CLK Cycle-to-Cycle Jitter Measured at 1.5V and all CLKs running the same frequency with Spread Spectrum enabled TCCJ3 CLK Cycle-to-Cycle Jitter Measured at 1.5V with CLKs running different frequencies but the same frequency within a Group and Sub-group and Spread Spectrum disabled TCCJ4 CLK Cycle-to-Cycle Jitter Measured at 1.5V with CLKs running different frequencies including within a Sub-group and Spread Spectrum disabled TCCJ5 CLK Cycle-to-Cycle Jitter Measured at 1.5V with CLKs running different frequencies including within a Sub-group and Spread Spectrum enabled SCLK www.DaTtaI2SCheet4U.com I2C Clock Period REF Measured at 1.5V Xin XIN being driven by an external clock source TDC REF Duty Cycle TRISE/TFALL REF Rise and Fall times Measured at 1.5V, See Figure 3 Measured from 0.4V to 2.4V, See Figure 3 TCCJ TXS REF Cycle-to-Cycle Jitter Power-on Hold Off Measured at 1.5V, See Figure 3 Outputs will be as shown in Figure 3 Table 7. Signal Loading Table Clock Name CLK REF Max Load (pF) 22 15 Min. 200 45 0.5 – – – – – – – 1.0 10 45 1 – – 66 MHz Typ. Max. – 333 – 55 – 3.0 – 150 – 150 – 150 200 – 200 – 400 – 600 –– – 18 – 55 –4 450 1000 – 1.2 Unit MHz % ns ps ps ps ps ps ps ps us MHz % ns ps ms Document #: 38-07542 Rev. ** Page 11 of 13 11 Page

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