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PDF SM55161A Data sheet ( Hoja de datos )
| Número de pieza | SM55161A | |
| Descripción | 262144 x 16 BIT VRAM MULTIPORT VIDEO RAM | |
| Fabricantes | Austin Semiconductor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de SM55161A (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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Austin Semiconductor, Inc.
VRAM
SM55161A
Production
262144 x 16 BIT VRAM
MULTIPORT VIDEO RAM
PIN ASSIGNMENT
(Top View)
AVAILABLE AS MILITARY
SPECIFICATIONS
• Military Processing Flow(SM Level)
• -55C to 125C temperature
64-Pin Ceramic Flatpack (HKC)
FEATURES
• Organization:
– DRAM: 262 144 by 16 Bits
– SAM: 512 by 16 Bits
• Dual-Port Accessibility – Simultaneous and Asynchronous
Access From the DRAM and SAM Ports
• Bidirectional Data-Transfer Function From the DRAM to
the Serial-Data Register, and from Serial Data Register to DRAM
• (8 x 8) x 2 Block Write feature for fast area fill
• Write-Per-Bit Feature for Selective Write to Each RAM I/O; Two
Write-Per-Bit Modes to Simplify System Design
• Byte-Write Control (CASL, CASU) Provides Flexibility
• Extended Data Output for Faster System Cycle Time
• Enhanced Page-Mode Operation for Faster Access
• CAS-Before-RAS (CBR) and Hidden-Refresh Modes
• Long Refresh Period: Every 8 ms (Maximum)
• Up to 50-MHz Uninterrupted Serial-Data Streams
• 512 Selectable Serial-Register Starting Locations
• SE-Controlled Register-Status QSF
• Split-Register-Transfer Read for Simplified Real-Time Register
Load
• Programmable Split-Register Stop Point
• 3-State Serial Outputs Allow Easy Multiplexing of Video-Data
Streams
• Pin-out Compatible upgrade from SM55161
• Compatible With JEDEC Standards
OPTIONS
• Timing
70ns access
75ns access
80ns access
• Package
68 pin PGA
64 pin Flatpack
MARKING
-70
-75
-80
GB
HKC
PIN DESCRIPTIONS
PIN
A0-A8
CASL\, CASU\
DQ0-DQ15
DSF
NC/GND
QSF
RAS\
SC
SE\
SQ0-SQ15
TRG\
VCC
VSS
WE\
DESCRIPTION
Address inputs
Column-Address Strobe/Byte Selects
DRAM Data I/O, Write Mask Data
Special Function Select
Special-Function Select
No Connect/Ground (NOTE: Not
connected internally to VSS)
Special-Function Output
Row-Address Strobe
Serial Clock
Serial Enable
Serial-Data Output
Output Enable, Transfer Select
5V Supply (TYP)
Ground
DRAM Write-Enable Select
• Operating Temperature Ranges
www.Data-SMheielitt4aUry.c(o-m55oC to +125oC)
- Industrial (-40oC to +85oC)
M suffix
I suffix
For more products and information
please visit our web site at
www.austinsemiconductor.com
SMJ55161A
Rev. 1.6 03/05
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
1
1 page  
Austin Semiconductor, Inc.
VRAM
SM55161A
Production
TABLE 1: DRAM & SAM FUNCTIONS
RAS\ FALL
CASx\
FALL
FUNCTION
CASx\2 TRG\ WE\ DSF DSF
Reserved (do not use)
CBR refresh (no reset) and stop-
point set4
CBR refresh (option reset)6
CBR refresh (no reset)7
L
L
L
L
LLLX
X L HX
XH L X
XHHX
ADDRESS
RAS\ CASX\3
X
Stop
point5
X
X
X
X
X
X
DQ0-DQ151
RAS\
X
CASL\
CASU\
WE\
X
MNE
CODE
---
X X CBRS
X X CBR
X X CBRN
Full-register-transfer read
H
L
H
L
X
Row Tap
Address Point
X
X RT
Split-register-transfer read
H
L
H
H
X
Row Tap
Address Point
X
X SRT
DRAM write
(nonpersistent write-per-bit)
H
H
L
L
L
Row Column Write
Address Address Mask
Valid
Data
RWM
DRAM block write
(nonpersistent write-per-bit)
H
H
L
L
H
Row
Address
Block
Address
A3-A8
Write
Mask
Column
Mask
BWM
DRAM write
(persistent write-per-bit)
H
H
L
L
L
Row Column
Address Address
X
Valid
Data
RWM
DRAM block write
(persistent write-per-bit)
H
H
L
L
H
Row
Address
Block
Address
A3-A8
X
Column
Mask
BWM
DRAM write (nonmasked)
H
H
H
L
L
Row Column
Address Address
X
Valid
Data
RW
DRAM block write (nonmasked)
H
H
H
L
H
Row
Address
Block
Address
A3-A8
X
Column
Mask
BW
Load write-mask register8
H
H
H
H
L
Refresh
Address
X
X
Write
Mask
LMR
Load color register
H
H
H
H
H
Refresh
Address
X
X
Color
Data
LCR
Masked Write Transfer9
H
L
L
L
X
Row Tap
Address Point
Write
Mask
X
MWT
Masked Split Write Transfer9
H
L
L
H
X
Row Tap
Address Point
Write
Mask
X MSWT
Masked Flash Write Transfer9
H
H
L
H
X
Row
Address
X
Write
Mask
---
FWM
LEGEND:
Col Mask = H: Write to address/column enabled
Write Mask = H: Write to I/O enabled
X = Don’t Care
NOTES:
1. DQ0–DQ15 are latched on either the first falling edge of CASx\ or the falling edge of WE\, whichever occurs later.
2. Logic L is selected when either or both CASL\ and CASU\ are low.
3. The column address and block address are latched on the first falling edge of CASx\.
4. CBRS cycle should be performed immediately after the power-up initialization cycle.
5. A0–A3, A8: don’t care; A4–A7: stop-point code
6. CBR refresh (option reset) mode ends persistent write-per-bit mode and stop-point mode.
www.D7a.taCSBhReerte4fUre.schom(no reset) mode does not end persistent write-per-bit mode or stop-point mode.
8. Load-write-mask-register cycle sets the persistent write-per-bit mode. The persistent write-per-bit mode is reset only by the CBR (option
reset) cycle.
9. MWT, MSWT, FWM function shown are for nonpersistent mask writes. These functions also support persistent mask write.
SMJ55161A
Rev. 1.6 03/05
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
5
5 Page 
Austin Semiconductor, Inc.
VRAM
SM55161A
Production
byte operation
Byte operation can be applied in DRAM-read cycles, write
cycles, block-write cycles, load-write-mask-register cycles, and
load-color-register cycles. In byte operation, the column
address (A0–A8) is latched at the first falling edge of CASx\. In
read cycles, CASL\ enables the lower byte (DQ0–DQ7) and
CASU\ enables the upper byte (DQ8–DQ15) (see Figure 4).
In byte-write operation, CASL enables data to be written
to the lower byte (DQ0–DQ7), and CASU\ enables data to be
written to the upper byte (DQ8–DQ15). In an early write cycle,
WE is brought low prior to both CASx\ signals, and data setup
and hold times for DQ0 –DQ15 are referenced to the first falling
edge of CASx\ (see Figure 5).
For late-write or read-modify-write cycles, WE\ is brought
low after either or both CASL\ and CASU\ fall. The data is
strobed in with data setup and hold times for DQ0 –DQ15
referenced to WE\ (see Figure 6).
FIGURE 4: Example of a Byte-Read Cycle
www.DataSheet4U.com
SMJ55161A
Rev. 1.6 03/05
11
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet SM55161A.PDF ] | |
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