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PDF CY8CLED16 Data sheet ( Hoja de datos )
| Número de pieza | CY8CLED16 | |
| Descripción | HB LED Controller | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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CY8CLED16
EZ-Color™ HB LED Controller
Features
■ HB LED Controller
❐ Configurable Dimmers Support up to 16
Independent LED Channels
❐ 8-32 Bits of Resolution per Channel
❐ Dynamic Reconfiguration Enables LED
Controller plus other Features; Battery
Charging, Motor Control…
■ Visual Embedded Design, PSoC Express
❐ LED Based Express Drivers
• Binning Compensation
• Temperature Feedback
• DMX512
■ PrISM Modulation Technology
❐ Reduces Radiated EMI
❐ Reduces Low Frequency Blinking
■ Powerful Harvard Architecture Processor
❐ M8C Processor Speeds to 24 MHz
❐ 3.0 to 5.25V Operating Voltage
❐ Operating Voltages down to 1.0V using
On-Chip Switch Mode Pump (SMP)
❐ Industrial Temperature Range: -40°C to +85°C
■ Programmable Pin Configurations
❐ 25 mA Sink on all GPIO
❐ Pull up, Pull down, High Z, Strong, or Open Drain Drive
Modes on all GPIO
❐ Up to eight Analog Inputs on GPIO
❐ Configurable Interrupt on all GPIO
■ Advanced Peripherals (PSoC Blocks)
❐ 16 Digital PSoC Blocks Provide:
• 8 to 32-Bit Timers, Counters, and PWMs
• Up to 2 Full-Duplex UART
• Multiple SPI™ Masters or Slaves
• Connectable to all GPIO Pins
❐ 12 Rail-to-Rail Analog PSoC Blocks Provide:
• Up to 14-Bit ADCs
• Up to 9-Bit DACs
• Programmable Gain Amplifiers
• Programmable Filters and Comparators
❐ Complex Peripherals by Combining Blocks
■ Flexible On-Chip Memory
❐ 32K Flash Program Storage 50,000 Erase/Write Cycles
❐ 2K SRAM Data Storage
❐ In-System Serial Programming (ISSP)
❐ Partial Flash Updates
❐ Flexible Protection Modes
❐ EEPROM Emulation in Flash
■ Complete Development Tools
❐ Free Development Software
• PSoC Designer™
• PSoC Express™
❐ Full-Featured, In-Circuit Emulator and
Programmer
❐ Full Speed Emulation
❐ Complex Breakpoint Structure
❐ 128 KBytes Trace Memory
EZ-Color HB LED Controller
Preliminary Data Sheet
www.DataSheet4U.com
Cypress Semiconductor Corporation
Document Number: 001-13105 Rev. **
•198 Champion Court•San Jose, CA 95134-1709•408-943-2600
Revised June 12, 2007
1 page  
CY8CLED16
Figure 2. Analog System Block Diagram
P0[7]
P0[6]
P0[5]
P0[4]
P0[3]
P0[1]
P0[2]
P0[0]
P2[3]
P2[1]
P2[6]
P2[4]
P2[2]
P2[0]
Array Input Configuration
ACI0[1:0]
ACI1[1:0]
ACI2[1:0]
ACI3[1:0]
ACB00
Block Array
ACB01
ACB02
ACB03
ASC10
ASD11
ASC12
ASD13
ASD20
ASC21
ASD22
ASC23
Additional System Resources
System Resources, some of which have been previously listed,
provide additional capability useful to complete systems.
Resources include a multiplier, decimator, switch mode pump,
low voltage detection, and power on reset. Statements
describing the merits of each system resource are presented
below.
■ Digital clock dividers provide three customizable clock
frequencies for use in applications. The clocks can be routed
to both the digital and analog systems. Additional clocks can
be generated using digital PSoC blocks as clock dividers.
■ Multiply accumulate (MAC) provides fast 8-bit multiplier with
32-bit accumulate, to assist in general math and digital filters.
■ The decimator provides a custom hardware filter for digital
signal, processing applications including the creation of Delta
Sigma ADCs.
■ The I2C module provides 100 and 400 kHz communication over
two wires. Slave, master, and multi-master modes are all
supported.
■ Low Voltage Detection (LVD) interrupts can signal the appli-
cation of falling voltage levels, while the advanced POR (Power
On Reset) circuit eliminates the need for a system supervisor.
■ An internal 1.3 voltage reference provides an absolute
reference for the analog system, including ADCs and DACs.
■ An integrated switch mode pump (SMP) generates normal
operating voltages from a single 1.2V battery cell, providing a
low cost boost converter.
Interface to
Digital System
RefHi
RefLo
AGND
Analog Reference
Reference
Generators
AGNDIn
RefIn
Bandgap
M8C Interface (Address Bus, Data Bus, Etc.)
www.DataSheet4U.com
Document Number: 001-13105 Rev. **
Page 5 of 39
5 Page 
CY8CLED16
Table 4. 48-Pin Part Pinout (QFN**)
Pin Type
Pin
No. Digital Analog Name
Description
1 IO
I P2[3] Direct switched capacitor block input.
2 IO
I P2[1] Direct switched capacitor block input.
3 IO
P4[7]
4 IO
P4[5]
5 IO
P4[3]
6 IO
P4[1]
7
Power
SMP Switch Mode Pump (SMP) connection to
external components required.
8 IO
P3[7]
9 IO
P3[5]
10 IO
P3[3]
11 IO
P3[1]
12 IO
P5[3]
13 IO
P5[1]
14 IO
P1[7] I2C Serial Clock (SCL).
15 IO
P1[5] I2C Serial Data (SDA).
16 IO
P1[3]
17 IO
P1[1]
Crystal (XTALin), I2C Serial Clock (SCL),
ISSP-SCLK*.
18
Power
Vss Ground connection.
19 IO
P1[0]
Crystal (XTALout), I2C Serial Data (SDA),
ISSP-SDATA*.
20 IO
P1[2]
21 IO
P1[4] Optional External Clock Input (EXTCLK).
22 IO
P1[6]
23 IO
P5[0]
24 IO
P5[2]
25 IO
P3[0]
26 IO
P3[2]
27 IO
P3[4]
28 IO
P3[6]
29
Input
XRES Active high external reset with internal pull
down.
30 IO
P4[0]
31 IO
P4[2]
32 IO
P4[4]
33 IO
P4[6]
34 IO
I P2[0] Direct switched capacitor block input.
35 IO
I P2[2] Direct switched capacitor block input.
36 IO
P2[4] External Analog Ground (AGND).
37 IO
P2[6] External Voltage Reference (VREF).
38 IO
I P0[0] Analog column mux input.
39 IO
IO P0[2] Analog column mux input and column output.
40 IO
IO P0[4] Analog column mux input and column output.
41 IO
I P0[6] Analog column mux input.
42
Power
Vdd Supply voltage.
43 IO
I P0[7] Analog column mux input.
44 IO
IO P0[5] Analog column mux input and column output.
45 IO
IO P0[3] Analog column mux input and column output.
A, I, P2[3]
A, I, P2[1]
P4[7]
P4[5]
P4[3]
P4[1]
SMP
P3[7]
P3[5]
P3[3]
P3[1]
P5[3]
1
2
3
4
5
6
7
8
9
10
11
12
48-Pin PSoC Device
MLF
(Top View)
36 P2[4], External AGND
35 P2[2], A, I
34 P2[0], A, I
33 P4[6]
32 P4[4]
31 P4[2]
30 P4[0]
29 XRES
28 P3[6]
27 P3[4]
26 P3[2]
25 P3[0]
www.DataSheet4U.com
Document Number: 001-13105 Rev. **
Page 11 of 39
11 Page | ||
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| PDF Descargar | [ Datasheet CY8CLED16.PDF ] | |
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