PDF AS5SP512K36DQ Data sheet ( Hoja de datos )

Número de pieza	AS5SP512K36DQ
Descripción	Plastic Encapsulated Microcircuit 18Mb
Fabricantes	Austin Semiconductor
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No Preview Available ! SSRAM Austin Semiconductor, Inc. AS5SP512K36DQ Plastic Encapsulated Microcircuit 18Mb, 512K x 36, Synchronous SRAM Pipeline Burst, Single Cycle Deselect FEATURES • Synchronous Operation in relation to the input Clock • 2 Stage Registers resulting in Pipeline operation • On chip address counter (base +3) for Burst operations • Self-Timed Write Cycles • On-Chip Address and Control Registers • Byte Write support • Global Write support • On-Chip low power mode [powerdown] via ZZ pin • Interleaved or Linear Burst support via Mode pin • Three Chip Enables for ease of depth expansion without Data Contention. • Two Cycle load, Single Cycle Deselect • Asynchronous Output Enable (OE\) • Three Pin Burst Control (ADSP\, ADSC\, ADV\) • 3.3V Core Power Supply • 3.3V/2.5V IO Power Supply • JEDEC Standard 100 pin TQFP Package, MS026-D/BHA • Available in Industrial, Enhanced, and Mil-Temperature Operating Ranges DQPc DQc DQc VDDQ VSSQ DQc DQc DQc DQc VSSQ VDDQ DQc DQc NC VDD NC VSS DQd DQd VDDQ VSSQ DQd DQd DQd DQd VSSQ VDDQ DQd DQd DQPd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 SSRAM [SPB] 80 DQPb 79 DQb 78 DQb 77 VDDQ 76 VSSQ 75 DQb 74 DQb 73 DQb 72 DQb 71 VSSQ 70 VDDQ 69 DQb 68 DQb 67 VSS 66 NC 65 VDD 64 ZZ 63 DQa 62 DQa 61 VDDQ 60 VSSQ 59 DQa 58 DQa 57 DQa 56 DQa 55 VSSQ 54 VDDQ 53 DQa 52 DQa 51 DQPa Fast Access Times Parameter Cycle Time Clock Access Time Output Enable Access Time Symbol tCYC tCD tOE www.DataSheet4U.com Block Diagram 200Mhz 5.0 3.0 3.0 166Mhz 6.0 3.5 3.5 133Mhz 7.5 4.0 4.0 OE\ ZZ CLK CE1\ CE2 CE3\ BWE\ BWx\ GW\ ADV ADSC\ ADSP\ MODE A0-Ax CONTROL BLOCK BURST CNTL. Address Registers Row Decode Column Decode I/O Gating and Control Memory Array x36 SBP ❑ Synchronous Pipeline Burst ❋ Two (2) cycle load ❋ One (1) cycle de-select ❋ One (1) cycle latency on Mode change Output Output Register Driver Input Register Units ns ns ns GENERAL DESCRIPTION ASI’s AS5SP512K36DQ is a 18Mb High Performance Synchronous Pipeline Burst SRAM, available in multiple temperature screening levels, fabricated using High Performance CMOS technology and is organized as a 512K x 36. It integrates address and control registers, a two (2) bit burst address counter supporting four (4) double-word transfers. Writes are internally self-timed and synchronous to the rising edge of clock. ASI’s AS5SP512K36DQ includes advanced control options including Global Write, Byte Write as well as an Asynchronous Output enable. Burst Cycle controls are DQx, DQPx handled by three (3) input pins, ADV, ADSP\ and ADSC\. Burst operation can be initiated with either the Address Status Processor (ADSP\) or Address Status Cache controller (ADSC\) inputs. Subsequent burst addresses are generated internally in the system’s burst sequence control block and are controlled by Address Advance AS5SP512K36DQ Rev. 2.5 09/08 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 1 1 page SSRAM Austin Semiconductor, Inc. AS5SP512K36DQ DC Electrical Characteristics (VDD=3.3v-5%/+10%, TA=Min. and Max temperatures of Screening level chosen Symbol VDD VDDQ VoH VoL VIH VIL IIL IZZL IOL IDD ISB1 ISB2 ISB3 ISB4 Parameter Power Supply Voltage I/O Supply Voltage Output High Voltage Output Low Voltage Input High Voltage Input Low Voltage Input Leakage (except ZZ) Input Leakage, ZZ pin Output Leakage Operating Current Automatic CE, Power Down Current - TTL inputs CMOS Standby TTL Standby Clock Running Test Conditions VDD=Min., IOH=-4mA VDD=Min., IOH=-1mA VDD=Min., IOL=8mA VDD=Min., IOL=1mA VDD=Max., VIN=VSS to VDD 3.3v 2.5v 3.3v 2.5v 3.3v 2.5v 3.3v 2.5v Output Disabled, VOUT=VSSQ to VDDQ VDD=Max., f=Max., IOH=0mA 5.0ns Cycle, 200 Mhz 6.0ns Cycle, 166 Mhz 7.5ns Cycle, 133 Mhz Max VDD, De-Selected, VIN>=VIH or VIN</=VIL 5.0ns Cycle, 200 Mhz f=fMAX=1/tCYC 6.0ns Cycle, 166 Mhz 7.5ns Cycle, 133 Mhz Max. VDD, Device deselected, VIN </=0.3V or VIN>/=VDDQ-0.3V f=fMAX=1/tCYC Device deselected; VDD=Max.; All Inputs </= VIL or VIH; All inputs static; CLK frequency = 0 Device deselected; VDD=Max.; All inputs < VSS+0.2v or VDD-0.2v; 5.0ns Cycle, 200 Mhz 6.0ns Cycle, 166 Mhz Cycle time (tKC)= Min. 7.5ns Cycle, 133 Mhz Min 3.135 2.375 2.4 2 2 1.7 -0.3 -0.3 -5 -30 -5 Max 3.630 VDD 0.4 0.4 VDD+0.3 VDD+0.3 0.8 0.7 5 30 5 350 300 275 Units V V V V V V V V V V uA uA uA mA mA mA 160 150 140 70 mA 80 mA Notes 1 1,5 1,4 1,4 1,4 1,4 1,2 1,2 1,2 1,2 3 3 135 mA 130 mA 125 mA Thermal Resistance Symbol Description Conditions Thermal Resistance TJA (Junction to Ambient) Test Conditions follow standard test methods and Thermal Resistance procedures for measuring thermal impedance, as www.DaTtJaCSheet4U.c(Joumnction to Top of Case, Top) per EIA/JESD51 Typical 1-Layer 31 9 Units 0C/W 0C/W Notes 6 6 Notes: [1] [2] [3] [4] [5] [6] All Voltages referenced to VSS (Logic Ground) Overshoot: VIH < +4.6V for t<tKC/2 for I<20mA Undershoot: VIL >-0.7V for t<tKC/2 for I<20mA Power-up: VIH <+3.6V and VDD<3.135V for t<200ms MODE and ZZ pins have internal pull-up resistors, and input leakage +/> +10uA The load used for VOH, VOL testing is shown in Figure-2 for 3.3v and 2.5V supplies. AC load current is higher than stated values, AC I/O curves can be made available upon request VDDQ should never exceed VDD, VDD and VDDQ can be connected together This parameter is sampled AS5SP512K36DQ Rev. 2.5 09/08 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 5 5 Page SSRAM Austin Semiconductor, Inc. AS5SP512K36DQ DOCUMENT TITLE Plastic Encapsulated Microcircuit , 18Mb, 512K x 36, Synchronous SRAM Pipeline Burst, Single Cycle Deselect REVISION HISTORY Rev # 2.5 History Release Date Updated pinout on page one, updated September 2008 max ratings & DC Electrical Characteristics Status Release www.DataSheet4U.com AS5SP512K36DQ Rev. 2.5 09/08 11 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 11 Page

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