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PDF AS5SP512K18DQ Data sheet ( Hoja de datos )
| Número de pieza | AS5SP512K18DQ | |
| Descripción | Plastic Encapsulated Microcircuit 9Mb | |
| Fabricantes | Austin Semiconductor | |
| Logotipo |  |
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Austin Semiconductor, Inc.
COTS PEM
AS5SP512K18DQ
SSRAM
Plastic Encapsulated Microcircuit
9Mb, 512K x 18, Synchronous SRAM
Pipeline Burst, Single Cycle Deselect
Features
• Synchronous Operation in relation to the input Clock
• 2 Stage Registers resulting in Pipeline operation
• On chip address counter (base +3) for Burst operations
• Self-Timed Write Cycles
• On-Chip Address and Control Registers
• Byte Write support
• Global Write support
• On-Chip low power mode [powerdown] via ZZ pin
• Interleaved or Linear Burst support via Mode pin
• Three Chip Enables for ease of depth expansion without Data
Contention.
• Two Cycle load, Single Cycle Deselect
• Asynchronous Output Enable (OE\)
• Three Pin Burst Control (ADSP\, ADSC\, ADV\)
• 3.3V Core Power Supply
• 3.3V/2.5V IO Power Supply
• JEDEC Standard 100 pin TQFP Package, MS026-D/BHA
• Available in Industrial, Enhanced, and Mil-Temperature
Operating Ranges
NC
NC
NC
VDDQ
VSSQ
NC
NC
DQb
DQb
VSSQ
VDDQ
DQb
DQb
NC
VDD
NC
VSS
DQb
DQb
VDDQ
VSSQ
DQb
DQb
DQPb
NC
VSSQ
VDDQ
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
SSRAM [SPB]
80 A
79 NC
78 NC
77 VDDQ
76 VSSQ
75 NC
74 DQPa
73 DQa
72 DQa
71 VSSQ
70 VDDQ
69 DQa
68 DQa
67 VSS
66 NC
65 VDD
64 ZZ
63 DQa
62 DQa
61 VDDQ
60 VSSQ
59 DQa
58 DQa
57 NC
56 NC
55 VSSQ
54 VDDQ
53 NC
52 NC
51 NC
Fast Access Times
Parameter
Cycle Time
Clock Access Time
Output Enable Access Time
Symbol
tCYC
tCD
tOE
www.DataSheet4U.com
Block Diagram
200Mhz
5.0
3.0
3.0
166Mhz
6.0
3.5
3.5
133Mhz
7.5
4.0
4.0
OE\
ZZ
CLK
CE1\
CE2
CE3\
BWE\
BWx\
GW\
ADV
ADSC\
ADSP\
MODE
A0-Ax
CONTROL
BLOCK
BURST CNTL.
Address
Registers
Row
Decode
Column
Decode
I/O Gating and Control
Memory Array
x18
SBP
❑ Synchronous Pipeline
Burst
❋ Two (2) cycle load
❋ One (1) cycle
de-select
❋ One (1) cycle latency
on Mode change
Output Output
Register Driver
Input
Register
Units
ns
ns
ns
General Description
ASI’s AS5SP512K18DQ is a 9.0Mb High Performance
Synchronous Pipeline Burst SRAM, available in multiple
temperature screening levels, fabricated using High Performance
CMOS technology and is organized as a 512K x 18. It integrates
address and control registers, a two (2) bit burst address counter
supporting four (4) double-word transfers. Writes are internally
self-timed and synchronous to the rising edge of clock.
ASI’s AS5SP512K18DQ includes advanced control options
including Global Write, Byte Write as well as an Asynchronous
DQx, DQPx Output enable. Burst Cycle controls are handled by three (3)
input pins, ADV, ADSP\ and ADSC\. Burst operation can be
initiated with either the Address Status Processor (ADSP\) or
Address Status Cache controller (ADSC\) inputs. Subsequent
burst addresses are generated internally in the system’s burst
sequence control block and are controlled by Address Advance
(ADV) control input.
AS5SP512K18DQ
Revision 1.0 04/04/04
Austin Semiconductor, Inc. reserves the right to change products or modify product specifications with appropriate notification
For Additional Products and Information visit out Web site at www.austinsemiconductor.com
1
1 page  
Austin Semiconductor, Inc.
COTS PEM
AS5SP512K18DQ
SSRAM
DC Electrical Characteristics (VDD=3.3v -5%/+10%,
TA= Min. and Max temperatures of Screening level chosen)
Symbol
Parameter
Test Conditions
VDD
Power Supply Voltage
VDDQ
I/O Supply Voltage
VoH
Output High Voltage
VDD=Min., IOH=-4mA
VDD=Min., IOH=-1mA
3.3v
2.5v
VoL
VIH
Output Low Voltage
Input High Voltage
VDD=Min., IOL=8mA
VDD=Min., IOL=1mA
3.3v
2.5v
3.3v
2.5v
VIL Input Low Voltage
3.3v
2.5v
IIL
Input Leakage (except ZZ)
VDD=Max., VIN=VSS to VDD
IZZL
Input Leakage, ZZ pin
IOL
Output Leakage
Output Disabled, VOUT=VSSQ to VDDQ
IDD
Operating Current
VDD=Max., f=Max.,
5.0ns Cycle, 200 Mhz
IOH=0mA
6.0ns Cycle, 166 Mhz
7.5ns Cycle, 133 Mhz
ISB1
Automatic CE. Power-down
Current -TTL inputs
Max. VDD, Device De-Selected,
VIN>/=VIH or VIN</=VIL
5.0ns Cycle, 200 Mhz
f=fMAX=1/tCYC
6.0ns Cycle, 166 Mhz
7.5ns Cycle, 133 Mhz
ISB2
Automatic CE. Power-down
Max. VDD, Device De-Selected, VIN</=0.3v or VIN>/=VDDQ-0.3v
ISB4
Current - CMOS Inputs
Automatic CE. Power-down
f=fMAX=1/tCYC
Max. VDD, Device De-Selected, VIN>/=VIH or VIN </= VIL, f=0
Current -TTL inputs
ISB3
Automatic CE. Power-down
Current - CMOS Inputs
Max. VDD, Device De-Selected, or
VIN</=0.3v or VIN >/=VDDQ-0.3v,
5.0ns Cycle, 200 Mhz
f-Max=1/tCYC
6.0ns Cycle, 166 Mhz
7.5ns Cycle, 133 Mhz
Thermal Resistance
Symbol
θJA
Description
Thermal Resistance
(Junction to Ambient)
Thermal Resistance
wwθwJ.CDataShee(tJ4uUn.cctoiomn to Top of Case, Top)
Conditions
Test Conditions follow standard test methods and
procedures for measuring thermal impedance, as
per EIA/JESD51
Min
3.135
2.375
2.4
2
2
1.7
-0.3
-0.3
-5
-30
-5
Max
3.630
VDD
0.4
0.4
VDD+0.3
VDD+0.3
0.8
0.7
5
30
5
250
220
185
Units
V
V
V
V
V
V
V
V
V
V
uA
uA
uA
mA
mA
mA
50 mA
50 mA
50 mA
30 mA
50 mA
Notes
1
1,5
1,4
1,4
1,4
1,4
1,2
1,2
1,2
1,2
3
3
40 mA
40 mA
40 mA
Typical
1-Layer
25
Units
0C/W
Notes
6
9 0C/W 6
Notes:
[1]
[2]
[3]
[4]
[5]
[6]
All Voltages referenced to VSS (Logic Ground)
Overshoot: VIH < +4.6V for t<tKC/2 for I<20mA
Undershoot: VIL >-0.7V for t<tKC/2 for I<20mA
Power-up: VIH <+3.6V and VDD<3.135V for t<200ms
MODE and ZZ pins have internal pull-up resistors, and input leakage +/> +10uA
The load used for VOH, VOL testing is shown in Figure-2 for 3.3v and 2.5V supplies.
AC load current is higher than stated values, AC I/O curves can be made available upon request
VDDQ should never exceed VDD, VDD and VDDQ can be connected together
This parameter is sampled
AS5SP512K18DQ
Revision 1.0 04/04/04
Austin Semiconductor, Inc. reserves the right to change products or modify product specifications with appropriate notification
For Additional Products and Information visit out Web site at www.austinsemiconductor.com
5
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet AS5SP512K18DQ.PDF ] | |
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