PDF AS5SP1M36DQ Data sheet ( Hoja de datos )

Número de pieza	AS5SP1M36DQ
Descripción	36Mb Pipelined Sync SRAM
Fabricantes	Austin Semiconductor
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No Preview Available ! AUSTIN SEMICONDUCTOR, INC. SSRAM Austin Semiconductor, Inc. AS5SP1M36DQ 36Mb Pipelined Sync SRAM FEATURES • Supports bus operation up to 200 MHz • Available speed grades are 200 and 166 MHz • Registered inputs and outputs for pipelined operation • 3.3V core power supply • 2.5V/3.3V I/O power supply • Fast clock-to-output times • Provide high-performance 3-1-1-1 access rate • User-selectable burst counter supporting Intel® • Pentium® interleaved or linear burst sequences • Separate processor and controller address strobes • Synchronous self-timed writes • Asynchronous output enable • Single Cycle Chip Deselect • Available in lead-free 100-pin TQFP package • IEEE 1149.1 JTAG-Compatible Boundary Scan • “ZZ” Sleep Mode Option OPTION MARKING Temperature Range Military Temp (-55oC to +125oC) /XT Industrial (-40oC to +85oC) /IT Enhanced (-40oC to +105oC) /ET FIGURE 1: PIN ASSIGNMENT (Top View) DQPC DQC DQc VDDQ VSSQ DQC DQC DQC DQC VSSQ VDDQ DQC DQC NC VDD NC VSS DQD DQD VDDQ VSSQ DQD DQD DQD DQD VSSQ VDDQ DQD DQD DQPD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 AS5SP1M36DQ CY7(1CM144x03A6V)33 (1M x 36) 80 DQPB 79 DQB 78 DQB 77 VDDQ 76 VSSQ 75 DQB 74 DQB 73 DQB 72 DQB 71 VSSQ 70 VDDQ 69 DQB 68 DQB 67 VSS 66 NC 65 VDD 64 ZZ 63 DQA 62 DQA 61 VDDQ 60 VSSQ 59 DQA 58 DQA 57 DQA 56 DQA 55 VSSQ 54 VDDQ 53 DQA 52 DQA 51 DQPA SELECTION GUIDE www.DatMaSahxeiemt4uUm.coAmccessTime MaximumOperatingCurrent MaximumCMOSStandbyCurrent 200MHz 3.2 425 120 166MH 3.4 375 120 Unit ns mA mA GENERAL DESCRIPTION The AS5SP1M36DQ SRAM integrates 1M x 36/2M x 18 and 512K x 72 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE1), depth- expansion Chip Enables (CE2 and CE3), Burst Control inputs (ADSC, ADSP, and ADV), Write Enables (BWX and BWE), and Global Write (GW). Asynchronous inputs include the Output Enable (OE) and the ZZ pin. Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor (ADSP) or Address Strobe Controller (ADSC) are active. Subsequent burst addresses can be internally generated as controlled by the Advance pin (ADV). Address, data inputs, and write controls are registered on- chip to initiate a self-timed Write cycle.This part supports Byte Write operations (see Pin Descriptions and Truth Table for further details). Write cycles can be one to two or four bytes wide as controlled by the byte write control inputs. GW when active LOW causes all bytes to be written. The AS5SP1M36DQ operates from a +3.3V core power supply while all outputs may operate with either a +2.5 or +3.3V supply. All inputs and outputs are JEDEC-standard JESD8-5-compatible. AS5SP1M36DQ Rev. 1.2 4/09 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 1 1 page AUSTIN SEMICONDUCTOR, INC. SSRAM Austin Semiconductor, Inc. AS5SP1M36DQ FUNCTIONAL OVERVIEW (continued) Burst Sequences The AS5SP1M36DQ provides a two-bit wraparound counter, fed by A1: A0, that implements either an interleaved or linear burst sequence. The interleaved burst sequence is designed specifically to support Intel Pentium applications. The linear burst sequence is designed to support processors that follow a linear burst sequence. The burst sequence is user selectable through the MODE input. Asserting ADV LOW at clock rise will automatically increment the burst counter to the next address in the burst sequence. Both Read and Write burst operations are supported. Sleep Mode The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation “sleep” mode. Two clock cycles are required to enter into or exit from this “sleep” mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the “sleep” mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering the “sleep” mode. CE1, CE2, CE3, ADSP, and ADSC must remain inactive for the duration of tZZREC after the ZZ input returns LOW. InterleavedBurstAddressTable (MODE=FloatingorVDD) First Second Third Address Address Address A1:A0 A1:A0 A1:A0 00 01 10 01 00 11 10 11 00 11 10 01 Fourth Address A1:A0 11 10 01 00 LinearBurstAddressTable (MODE=GND) First Second Third Address Address Address A1:A0 A1:A0 A1:A0 00 01 10 01 00 11 10 11 00 11 10 01 Fourth Address A1:A0 11 10 01 00 ZZModeElectricalCharacteristics Parameter Description IDDZZ Sleepmodestandbycurrent www.DattaZZSSheet4U.com DeviceoperationtoZZ tZZREC ZZrecoverytimes tZZI ZZactivetosleepcurrent tRZZI ZZinactivetoexitsleepcurrent TestConditions ZZшVDDͲ0.2V ZZшVDDͲ0.2V ZZч0.2V Thisparameterissamples Thisparameterissamples Min 2tCYC 0 Max 2tCYC 2tCYC Unit mA ns ns ns ns AS5SP1M36DQ Rev. 1.2 4/09 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 5 5 Page AUSTIN SEMICONDUCTOR, INC. SSRAM Austin Semiconductor, Inc. AS5SP1M36DQ TAODCElectricalCharacteristicsandOperatingConditons 0oC<TA<+70oC;VDD=3.135to3.6Vunlessotherwisenoted) [12] Parameter VOH1 VOH2 VOL1 VOL2 VIH VIL IX Description OutputHIGHVoltage OutputHIGHVoltage OutputLOWVoltage OutputLOWVoltage InputHIGHVoltage InputLOWVoltage InputLoadCurrent TestConditions IOH=Ͳ4.0mA,VDDQ=3.3V IOH=Ͳ1.0mA,VDDQ=2.5V IOH=Ͳ100μA VDDQ=3.3V VDDQ=2.5V IOL=8.0mA VDDQ=3.3V IOL=1.0mA VDDQ=2.5V IOH=100μA VDDQ=3.3V VDDQ=2.5V VDDQ=3.3V VDDQ=2.5V VDDQ=3.3V GNDчVINчVDDQ VDDQ=2.5V Min Max Unit 2.4 V 2.0 V 2.9 V 2.1 V 0.4 V 0.4 V 0.2 V 0.2 V 2.0 VDD+0.3 1.7 VDD+0.3 Ͳ0.3 0.8 V V V Ͳ0.3 0.7 Ͳ5 5 V μA IdentificationRegisterDefinitions InstructionField RevisionNumber(31:29) DeviceDepth(28:24)[13] Architecture/MemoryType(23:18) www.DataSheet4U.com BusWidth/Density(17:12) JEDECIDCode(11:1) + IDRegisterPresenceIndicator(0) 1Mx36 000 Description Describestheversionnumber 01011 ReservedforInternalUse 000000 Definesmemorytypeandarchitecture 100111 Defineswidthanddensity 00000110100 AllowsuniqueidentificationofSRAMvendor 1 IndicatesthepresenceofanIDregister ScanRegisterSizes RegisterName Instruction Bypass ID BitSize(x36) 3 1 32 Notes: 12. All voltages referenced to VSS (GND). 13. Bit #24 is '1' in the ID Register Definitions for both 2.5V and 3.3V versions of this device. + Austin Semiconductor uses Cypress die so this code reflects Cypress. AS5SP1M36DQ Rev. 1.2 4/09 11 Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. 11 Page

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