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PDF LTC4215-1 Data sheet ( Hoja de datos )
| Número de pieza | LTC4215-1 | |
| Descripción | Hot Swap Controller | |
| Fabricantes | Linear Technology | |
| Logotipo |  |
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FEATURES
n Allows Safe Insertion into Live Backplane
n 8-Bit ADC Monitors Current and Voltage
n I2C/SMBus Interface
n Wide Operating Voltage Range: 2.9V to 15V
n dI/dt Controlled Soft-Start
n Circuit Breaker Timeout: 20μs (LTC4215-1) or
420μs (LTC4215-3)
n Three General Purpose Outputs
n High Side Drive for External N-channel MOSFET
n No External Gate Capacitor Required
n Input Overvoltage/Undervoltage Protection
n Optional Latchoff or Auto-Retry After Faults
n Alerts Host After Faults
n Inrush Current Limit with Foldback
n Available in 24-Pin (4mm × 5mm) QFN
APPLICATIONS
n Live Board Insertion
n Electronic Circuit Breakers
n Computers, Servers
n Platform Management
LTC4215-1/LTC4215-3
Hot Swap Controller with
I2C Compatible Monitoring
DESCRIPTION
The LTC®4215-1/LTC4215-3 Hot Swap™ controllers allow
a board to be safely inserted and removed from a live
backplane. Using an external N-channel pass transistor,
board supply voltage and inrush current are ramped up at
an adjustable rate. An I2C interface and onboard ADC allow
for monitoring of load current, voltage and fault status.
The device features adjustable foldback current limit and
a soft-start pin that sets the dI/dt of the inrush current.
An I2C interface may configure the part to latch off or
automatically restart after the LTC4215-1/LTC4215-3
detect a current limit fault.
The controller has additional features to interrupt the host
when a fault has occurred, provide three general purpose
outputs, notify when output power is good, detect insertion
of a load card, and power-up either automatically upon
insertion or wait for an I2C command to turn on.
The LTC4215-1 has a 20μs circuit breaker filter for applica-
tions that require a fast fault response time. The LTC4215-3
has an extended 420μs circuit breaker filter for applications
where supply transients may exceed 20μs.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. Hot Swap is a trademark of Linear Technology Corporation. All other
trademarks are the property of their respective owners. Protected by U.S. Patent 7330065.
TYPICAL APPLICATION
12V Application With 5A Circuit Breaker
Start-Up Waveform
12V
SDA
SCL
GND
BACKPLANE PLUG-IN
CARD
0.1μF
3.4k
P6KE16A
34.8k
0.005Ω FDC653N
VOUT
+ 12V
CL 30.1k
10Ω
1.18k
3.57k
UV VDD SENSE+ SENSE– GATE SOURCE
OV FB
SDAI
SDAO
SCL
ADR0
ADR1
LTC4215-1
GPIO1
GPIO2
GPIO3
ADIN
INTVCC
ON TIMER SS
GND EN
POWERGOOD
RESET
OK LED
MEASURED
VOLTAGE
0.1μF
68nF
4215 TA01a
VDD
10V/DIV
INRUSH
CURRENT
2.5A/DIV
VOUT
10V/DIV
CONTACT
BOUNCE
VGPIO1
10V/DIV
5k PULL-UP TO VDD
CL = 12000μF
40ms/DIV
42151 TA01b
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1
1 page  
LTC4215-1/LTC4215-3
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VDD = 12V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN TYP MAX UNITS
VSDA,SCL(TH) SDA, SCL Input Threshold
ISDA,SCL(OH)
SDA, SCL Input Current
VSDA(OL)
SDA Output Low Voltage
I2C Interface Timing
SCL, SDA = 5V
ISDA = 3mA
l 1.3 1.7 1.9
l ±1
l 0.2 0.4
V
μA
V
fSCL(MAX)
tBUF(MIN)
tHD,STA(MIN)
tSU,STA(MIN)
tSU,STO(MIN)
tHD,DAT(MIN)
tHD,DATO
tSU,DAT(MIN)
tSP
CX
SCL Clock Frequency
Bus Free Time Between Stop/Start Condition
Hold Time After (Repeated) Start Condition
Repeated Start Condition Set-Up Time
Stop Condition Set-Up Time
Data Hold Time (Input)
Data Hold Time (Output)
Data Set-Up Time
Suppressed Spike Pulse Width
SCL, SDA Input Capacitance
Operates with fSCL ≤ fSCL(MAX)
SDAI Tied to SDAO (Note 6)
l 400 1000
l 0.12 1.3
l 30 600
l 30 600
l 140 600
l 30 100
l 300 500 900
l 30 600
l 50 110 250
l 10
kHz
μs
ns
ns
ns
ns
ns
ns
ns
pF
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All currents into pins are positive; all voltages are referenced to
GND unless otherwise specified.
Note 3: An internal clamp limits the GATE pin to a minimum of 5V above
SOURCE. Driving this pin to voltages beyond the clamp may damage the
device.
Note 4: Offset error is the offset voltage measured from 1LSB when the
output code flickers between 0000 0000 and 0000 0001.
Note 5: Integral nonlinearity is defined as the deviation of a code from a
precise analog input voltage. Maximum specifications are limited by the
LSB step size and the single shot measurement. Typical specifications are
measured from the 1/4, 1/2 and 3/4 areas of the quantization band.
Note 6: Guaranteed by design and not subject to test.
TYPICAL PERFORMANCE CHARACTERISTICS. TA = 25°C, VDD = 12V unless otherwise noted.
IDD vs VDD
4
3
2
1
INTVCC vs VDD
4.0
3.5
3.0
INTVCC vs ILOAD
4
VDD = 12V, 5V
3
VDD = 3.3V
2
1
0
0 5 10 15 20 25
VDD (V)
4215 G01
2.5
2.5
3.0 3.5
INTVCC (V)
4.0
4215 G02
0
02
46
ILOAD (mA)
8 10
4215 G03
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5 Page 
LTC4215-1/LTC4215-3
OPERATION
The LTC4215-1/LTC4215-3 are designed to turn a board’s
supply voltage on and off in a controlled manner, allowing
the board to be safely inserted or removed from a live
backplane. During normal operation, the charge pump
and gate driver turn on an external N-channel MOSFET’s
gate to pass power to the load. The gate driver uses a
charge pump that derives its power from the VDD pin.
Also included in the gate driver is an internal 6.5V GATE-
to-SOURCE clamp. During start-up the inrush current is
tightly controlled by using current limit foldback, soft start
dI/dt limiting and output dV/dt limiting.
The current sense (CS) amplifier monitors the load current
using the difference between the SENSE+ and SENSE– pin
voltages. The CS amplifier limits the current in the load by
pulling back on the GATE-to-SOURCE voltage in an active
control loop when the sense voltage exceeds the com-
manded value. The CS amplifier requires 20μA input bias
current from both the SENSE+ and the SENSE– pins.
A short circuit on the output to ground results in excessive
power dissipation during active current limiting. To limit
this power, the CS amplifier regulates the voltage between
the SENSE+ and SENSE– pins at 75mV.
If an overcurrent condition persists, the internal circuit
breaker (CB) registers a fault when the sense voltage
exceeds 25mV for more than 20μs in the case of the
LTC4215-1 or 420μs in the case of the LTC4215-3. This
indicates to the logic that it is time to turn off the GATE
to prevent overheating. At this point the start-up TIMER
capacitor voltage ramps down using the 2μA current
source until the voltage drops below 0.2V (comparator
TM1) which tells the logic that the pass transistor has
cooled and it is safe to turn it on again if overcurrent
auto-retry is enabled. If the TIMER pin is tied to INTVCC,
the cool-down time defaults to 5 seconds on an internal
system timer in the logic.
The output voltage is monitored using the FB pin and the
Power Good (PG) comparator to determine if the power
is available for the load. The power good condition can be
signaled by the GPIO1 pin using an open-drain pull-down
transistor. The GPIO1 pin may also be configured to signal
power bad, or as a general purpose input (GP comparator),
or a general purpose open drain output.
GPIO2 and GPIO3 may also be configured as a general
purpose inputs or general purpose open drain outputs.
GPIO2 may also be configured to generate interrupts
when faults occur.
The Functional Diagram shows the monitoring blocks of
the LTC4215-1/LTC4215-3. The group of comparators on
the left side includes the undervoltage (UV), overvoltage
(OV), reset (RST), enable (EN) and (ON) comparators.
These comparators determine if the external conditions
are valid prior to turning on the GATE. But first the two
undervoltage lockout circuits, UVLO1 and UVLO2, validate
the input supply and the internally generated 3.1V supply,
INTVCC. UVLO2 also generates the power-up initialization
to the logic circuits as INTVCC crosses this rising threshold.
If the fixed internal overvoltage comparator, OV2, detects
that VDD is greater than 15.6V, the part immediately gener-
ates an overvoltage fault and turns the GATE off.
Included in the LTC4215-1/LTC4215-3 is an 8-bit A/D
converter. The converter has a 3-input multiplexer to
select between the ADIN pin, the SOURCE pin and the
VDD – SENSE voltage.
An I2C interface is provided to read the A/D registers. It
also allows the host to poll the device and determine if
faults have occurred. If the GPIO2 line is configured as an
ALERT interrupt, the host is enabled to respond to faults
in real time. The typical SDA line is divided into an SDAI
(input) and SDAO (output). This simplifies applications
using an optoisolator driven directly from the SDAO out-
put. An application which uses optoisolation is shown in
the Typical Applications section. The I2C device address
is decoded using the ADR0 and ADR1 pins. These inputs
have three states each that decode into a total of 9 device
addresses.
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11
11 Page | ||
| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet LTC4215-1.PDF ] | |
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