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PDF PH955L Data sheet ( Hoja de datos )

Número de pieza PH955L
Descripción N-channel TrenchMOS logic level FET
Fabricantes NXP Semiconductors 
Logotipo NXP Semiconductors Logotipo



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No Preview Available ! PH955L Hoja de datos, Descripción, Manual

PH955L
N-channel TrenchMOS logic level FET
Rev. 02 — 19 February 2009
Product data sheet
1. Product profile
1.1 General description
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using TrenchMOS technology. This product is designed and qualified for use in
computing, communications, consumer and industrial applications only.
1.2 Features and benefits
„ Low conduction losses due to low
on-state resistance
„ Suitable for logic level gate drive
sources
1.3 Applications
„ DC-to-DC convertors
„ General purpose power switching
„ Motors, lamps and solenoids
„ Portable equipment
1.4 Quick reference data
Table 1. Quick reference
Symbol Parameter
Conditions
VDS drain-source voltage Tj 25 °C; Tj 150 °C
ID drain current
Tmb = 25 °C; VGS = 5 V;
see Figure 1; see Figure 3
Ptot total power
dissipation
Tmb = 25 °C; see Figure 2
Dynamic characteristics
QGD
gate-drain charge VGS = 5 V; ID = 25 A;
VDS = 44 V; Tj = 25 °C;
see Figure 11; see Figure 12
Static characteristics
RDSon
drain-source
VGS = 10 V; ID = 25 A;
on-state resistance Tj = 25 °C; see Figure 10
Min Typ Max Unit
- - 55 V
- - 62.5 A
- - 62.5 W
- 16.4 - nC
- 6.2 8.3 m

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PH955L pdf
NXP Semiconductors
PH955L
N-channel TrenchMOS logic level FET
5. Thermal characteristics
Table 5.
Symbol
Rth(j-mb)
Thermal characteristics
Parameter
Conditions
thermal resistance from see Figure 4
junction to mounting
base
Min Typ Max Unit
- - 2 K/W
10
Zth(j-mb)
(K/W)
1
δ = 0.5
0.2
0.1
0.05
10-1
0.02
single pulse
10-2
003aaa778
P δ = tp
T
10-3
10-5
10-4
10-3
10-2
tp
T
t
10-1
1
tp (s)
Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration
PH955L_2
Product data sheet
Rev. 02 — 19 February 2009
© NXP B.V. 2009. All rights reserved.
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PH955L arduino
NXP Semiconductors
PH955L
N-channel TrenchMOS logic level FET
8. Revision history
Table 7. Revision history
Document ID
Release date Data sheet status
Change notice
Supersedes
PH955L_2
Modifications:
20090219
Product data sheet
-
PH955L_1
The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
Legal texts have been adapted to the new company name where appropriate.
PH955L_1
(9397 750 14557)
20050301
Product data sheet
-
-
PH955L_2
Product data sheet
Rev. 02 — 19 February 2009
© NXP B.V. 2009. All rights reserved.
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