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PDF IDTCSPF2510C Data sheet ( Hoja de datos )
| Número de pieza | IDTCSPF2510C | |
| Descripción | 3.3V PHASE-LOCK LOOP CLOCK DRIVER | |
| Fabricantes | Integrated Device Technology | |
| Logotipo |  |
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IDTCSPF2510C
3.3V PHASE-LOCK LOOP CLOCK DRIVER
www.DataSheet4U.com
3.3V PHASE-LOCK LOOP
CLOCK DRIVER
0ºC TO 85ºC TEMPERATURE RANGE
IDTCSPF2510C
FEATURES:
• Phase-Lock Loop Clock Distribution for Synchronous DRAM
Applications
• Distributes one clock input to one bank of ten outputs
• Output enable bank control
• External feedback (FBIN) pin is used to synchronize the output
to the clock input signal
• On-chip series damping resistors with each driver
• No external RC network required for PLL loop stability
• Operates at 3.3V VDD
• tpd Phase Error at 133MHz: < ±150ps
• Jitter (cycle-cycle)(peak-to-peak) at 66MHz to 133MHz: | 70 | ps
• Spread Spectrum Compatible
• Operating frequency 25MHz to 140MHz
• Fully conforms to PC133 specifications
• Available in 24-Pin TSSOP package
DESCRIPTION:
The IDTCSPF2510C is a high performance, low-skew, low-jitter,
phase-lock loop (PLL) clock driver. It uses a PLL to precisely align, in both
FUNCTIONAL BLOCK DIAGRAM
frequency and phase, the feedback (FBOUT) output to the clock (CLK) input
signal. It is specifically designed for use with synchronous DRAMs. The
CSPF2510C operates at 3.3V and provides integrated series-damping
resistors that make it ideal for driving point-to-point loads, single or dual.
One bank of ten outputs provide low-skew, low-jitter copies of CLK. Output
signal duty cycles are adjusted to 50 percent, independent of the duty cycle
at CLK. The outputs can be enabled or disabled via the control G input. When
the G input is high, the outputs switch in phase and frequency with CLK; when
the G input is low, the outputs are disabled to the logic-low state.
Unlike many products containing PLLs, the CSPF2510C does not require
external RC networks. The loop filter for the PLL is included on-chip,
minimizing component count, board space, and cost.
Because it is based on PLL circuitry, the CSPF2510C requires a
stabilization time to achieve phase lock of the feedback signal to the reference
signal. This stabilization time is required, following power up and application
of a fixed-frequency, fixed-phase signal at CLK, as well as following any
changes to the PLL reference or feedback signals. The PLL can be
bypassed for the test purposes by strapping AVDD to ground.
The CSPF2510C is characterized for operation from 0°C to +85°C. This
device is also available (on special order) in Industrial (-40°C to +85°C)
temperatures. See Ordering Information for more details.
11
G
3
Y0
4
Y1
5
Y2
8
Y3
9
Y4
CLK
24
F B IN
13
AVDD
23
PLL
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
0ºC TO 85ºC TEMPERATURE RANGE
c 2002 Integrated Device Technology, Inc.
1
15
Y5
16
Y6
17
Y7
20
Y8
21
Y9
12
FBOUT
AUGUST 2002
DSC-5409/6
1 page  
IDTCSPF2510C
3.3V PHASE-LOCK LOOP CLOCK DRIVER
www.DataSheet4U.com
PARAMETER MEASUREMENT INFORMATION(2)
0ºC TO 85ºC TEMPERATURE RANGE
From Output
Under Test
CL = 25pF(1)
500Ω
Load Circuit Waveforms
Input
See Note 5
tPHASE ERROR
Output
or
FBIN
2V
0.4V
tR
See Note 5
tF
Load Voltage Waveforms
Propagation Delay Times
PHASE ERROR AND SKEW CALCULATIONS (3,4,5)
3V
0V
VOH
2V
0.4V
VOL
CLK
CSPF2510C
Y
CL = 25pF (1)
FBIN
CF
FBOUT
PCBTRACE
500Ω
on each
Y output
CLK
FBIN
FBOUT
Any Y
Any Y
Any Y
tPHASE ERROR
tSK(o)
tSK(o)
NOTES:
1. CL includes probe and jig capacitance.
2. All inputs pulses are supplied by generators having the following characteristics: PRR ≤ 100MHz, ZO = 50Ω, tR ≤ 1.2 ns, tF ≤ 1.2 ns.
3. The outputs are measured one at a time with one transition per measurement.
4. Phase error measurements require equal loading at outputs Y and FBOUT. CF = CL – CFBIN – CPCBTRACE; CFBIN ≅ 6pF.
5. V threshold set at 1.5V across Voltage/Temp operating range.
5
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet IDTCSPF2510C.PDF ] | |
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