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PDF LMK04000 Data sheet ( Hoja de datos )
| Número de pieza | LMK04000 | |
| Descripción | Low-Noise Clock Jitter Cleaner | |
| Fabricantes | National Semiconductor | |
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LMK04000 Family
July 24, 2009
Low-Noise Clock Jitter Cleaner with Cascaded PLLs
1.0 General Description
The LMK04000 family of precision clock conditioners pro-
vides low-noise jitter cleaning, clock multiplication and distri-
bution without the need for high-performance voltage con-
trolled crystal oscillators (VCXO) module. Using a cascaded
PLLatinum™ architecture combined with an external crystal
and varactor diode, the LMK04000 family provides sub-200
femtosecond (fs) root mean square (RMS) jitter performance.
The cascaded architecture consists of two high-performance
phase-locked loops (PLL), a low-noise crystal oscillator cir-
cuit, and a high-performance voltage controlled oscillator
(VCO). The first PLL (PLL1) provides a low-noise jitter cleaner
function while the second PLL (PLL2) performs the clock gen-
eration. PLL1 can be configured to either work with an exter-
nal VCXO module or use the integrated crystal oscillator with
an external crystal and a varactor diode. When used with a
very narrow loop bandwidth, PLL1 uses the superior close-in
phase noise (offsets below 50 kHz) of the VCXO module or
the crystal to clean the input clock. The output of PLL1 is used
as the clean input reference to PLL2 where it locks the inte-
grated VCO. The loop bandwidth of PLL2 can be optimized
to clean the far-out phase noise (offsets above 50 kHz) where
the integrated VCO outperforms the VCXO module or crystal
used in PLL1.
The LMK04000 family features dual redundant inputs, five
differential outputs, and an optional default-clock upon power
up. The input block is equipped with loss of signal detection
and automatic or manual selection of the reference clock.
Each clock output consists of a programmable divider, a
phase synchronization circuit, a programmable delay, and an
LVDS, LVPECL, or LVCMOS output buffer. The default start-
up clock is available on CLKout2 and it can be used to provide
an initial clock for the field-programmable gate array (FPGA)
or microcontroller that programs the jitter cleaner during the
system power up sequence.
2.0 Features
■ Cascaded PLLatinum PLL Architecture
— PLL1
■ Phase detector rate of up to 40 MHz
■ Integrated Low-Noise Crystal Oscillator Circuit
■ Dual redundant input reference clock with LOS
— PLL2
■ Normalized [1 Hz] PLL noise floor of -224 dBc/Hz
■ Phase detector rate up to 100 MHz
■ Input frequency-doubler
■ Integrated Low-Noise VCO
■ Ultra-Low RMS Jitter Performance
— 150 fs RMS jitter (12 kHz – 20 MHz)
— 200 fs RMS jitter (100 Hz – 20 MHz)
■ LVPECL/2VPECL, LVDS, and LVCMOS outputs
■ Support clock rates up to 1080 MHz
■ Default Clock Output (CLKout2) at power up
■ Five dedicated channel divider and delay blocks
■ Pin compatible family of clocking devices
■ Industrial Temperature Range: -40 to 85 °C
■ 3.15 V to 3.45 V operation
■ Package: 48 pin LLP (7.0 x 7.0 x 0.8 mm)
3.0 Target Applications
■ Data Converter Clocking
■ Wireless Infrastructure
■ Networking, SONET/SDH, DSLAM
■ Medical
■ Military / Aerospace
■ Test and Measurement
■ Video
PLLatinum™ is a trademark of National Semiconductor Corporation.
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 2009 National Semiconductor Corporation 300271
30027140
www.national.com
1 page  
16.9.1 PLL1_N: PLL1_N Counter ........................................................................................... 35
www.DataShe1e6t4.U9.c2omPLL1_R: PLL1_R Counter ........................................................................................... 36
16.9.3 PLL1 Charge Pump Current Gain (PLL1_CP_GAIN) and Polarity Control
(PLL1_CP_POL) ................................................................................................................ 36
16.10 REGISTER 13 .................................................................................................................... 36
16.10.1 EN_PLL2_XTAL: Crystal Oscillator Option Enable ......................................................... 36
16.10.2 EN_Fout: Fout Power Down Bit .................................................................................. 36
16.10.3 CLK Global Enable: Clock Global enable bit ................................................................. 36
16.10.4 POWERDOWN Bit -- Device Power Down .................................................................... 36
16.10.5 EN_PLL2 REF2X: PLL2 Frequency Doubler control bit .................................................. 36
16.10.6 PLL2 Internal Loop Filter Component Values ................................................................ 36
16.10.7 PLL1 CP TRI-STATE and PLL2 CP TRI-STATE ............................................................ 37
16.11 REGISTER 14 .................................................................................................................... 37
16.11.1 OSCin_FREQ: PLL2 Oscillator Input Frequency Register ............................................... 37
16.11.2 PLL2_R: PLL2_R Counter .......................................................................................... 37
16.11.3 PLL_MUX: LD Pin Selectable Output ........................................................................... 37
16.12 REGISTER 15 .................................................................................................................... 38
16.12.1 PLL2_N: PLL2_N Counter .......................................................................................... 38
16.12.2 PLL2_CP_GAIN: PLL2 Charge Pump Current and Output Control ................................... 38
16.12.3 VCO_DIV: PLL2 VCO Divide Register ......................................................................... 38
17.0 Application Information ................................................................................................................. 39
17.1 SYSTEM LEVEL DIAGRAM ................................................................................................... 39
17.2 LDO BYPASS AND BIAS PIN ................................................................................................ 40
17.3 LOOP FILTER ..................................................................................................................... 40
17.4 CURRENT CONSUMPTION / POWER DISSIPATION CALCULATIONS ..................................... 43
17.5 POWER SUPPLY CONDITIONING ........................................................................................ 43
17.6 THERMAL MANAGEMENT ................................................................................................... 43
17.7 OPTIONAL CRYSTAL OSCILLATOR IMPLEMENTATION (OSCin/OSCin*) ................................. 44
17.8 TERMINATION AND USE OF CLOCK OUTPUT (DRIVERS) ..................................................... 47
17.8.1 Termination for DC Coupled Differential Operation .......................................................... 47
17.8.2 Termination for AC Coupled Differential Operation .......................................................... 47
17.8.3 Termination for Single-Ended Operation ........................................................................ 48
17.9 DRIVING CLKin AND OSCin INPUTS ..................................................................................... 49
17.9.1 Driving CLKin Pins with a Differential Source .................................................................. 49
17.9.2 Driving CLKin Pins with a Single-Ended Source .............................................................. 49
17.10 ADDITIONAL OUTPUTS WITH AN LMK04000 FAMILY DEVICE .............................................. 49
17.11 OUTPUT CLOCK PHASE NOISE PERFORMANCE VS. VCXO PHASE NOISE .......................... 49
18.0 Physical Dimensions .................................................................................................................... 53
19.0 Ordering Information .................................................................................................................... 53
5 www.national.com
5 Page 
Symbol
www.DataSheet4U.com
fPD
ICPout1 SOURCE
ICPout1 SINK
ICPout1 %MIS
ICPout1VTUNE
ICPout1 %TEMP
PLL1 ICPout1 TRI
fOSCin
SLEWOSCin
VOSCin (Single-ended)
VOSCin (Differential)
Parameter
Conditions
PLL1 Specifications
PLL1 Phase Detector
Frequency
VCPout1 = VCC/2,
PLL1_CP_GAIN = 100b
VCPout1 = VCC/2,
PLL1_CP_GAIN = 101b
VCPout1 = VCC/2,
PLL1_CP_GAIN = 110b
PLL1 Charge Pump Source
Current (Note 11)
VCPout1 = VCC/2,
PLL1_CP_GAIN = 111b
PLL1_CP_GAIN = 000b
PLL1_CP_GAIN = 001b
VCPout1=VCC/2,
PLL1_CP_GAIN = 010b
VCPout1=VCC/2,
PLL1_CP_GAIN = 011b
VCPout1=VCC/2,
PLL1_CP_GAIN = 100b
VCPout1=VCC/2,
PLL1_CP_GAIN = 101b
VCPout1=VCC/2,
PLL1_CP_GAIN = 110b
PLL1 Charge Pump Sink
Current (Note 11)
VCPout1=VCC/2,
PLL1_CP_GAIN = 111b
PLL1_CP_GAIN = 000b
PLL1_CP_GAIN = 001b
VCPout1=VCC/2,
PLL1_CP_GAIN = 010b
VCPout1=VCC/2,
PLL1_CP_GAIN = 011b
Charge Pump Sink / Source
Mismatch
VCPout1 = VCC/2, T = 25 °C
Magnitude of Charge Pump
Current vs. Charge Pump
Voltage Variation
0.5 V < VCPout1 < VCC - 0.5 V
TA = 25 °C
Charge Pump Current vs.
Temperature Variation
Charge Pump TRI-
STATE®Leakage Current
0.5 V < VCPout < VCC - 0.5 V
PLL2 Reference Input (OSCin) Specifications
PLL2 Reference Input
(Note 12)
EN_PLL2_REF 2X = 0
(Note 13)
EN_PLL2_REF 2X = 1
PLL2 Reference Clock
minimum slew rate on OSCin
20% to 80%
Input Voltage for OSCin or
OSCin*
AC coupled; Single-ended
(Unused pin AC coupled to
GND)
Differential voltage swing
AC coupled
Min
0.15
0.2
0.4
Typ
25
50
100
400
NA
NA
20
80
-25
-50
-100
-400
NA
NA
-20
-80
3
4
4
0.5
Max Units
40 MHz
µA
µA
10 %
%
%
5 nA
250
MHz
50
V/ns
2.0 Vpp
3.1 Vpp
11 www.national.com
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| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet LMK04000.PDF ] | |
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