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Número de pieza | 74AUP1G04 | |
Descripción | Low-power inverter | |
Fabricantes | NXP Semiconductors | |
Logotipo | ||
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74AUP1G04
Low-power inverter
Rev. 02 — 28 June 2006
Product data sheet
1. General description
The 74AUP1G04 is a high-performance, low-power, low-voltage, Si-gate CMOS device,
superior to most advanced CMOS compatible TTL families.
Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall
times across the entire VCC range from 0.8 V to 3.6 V.
This device ensures a very low static and dynamic power consumption across the entire
VCC range from 0.8 V to 3.6 V.
This device is fully specified for partial Power-down applications using IOFF.
The IOFF circuitry disables the output, preventing the damaging backflow current through
the device when it is powered down.
The 74AUP1G04 provides the single inverting buffer.
2. Features
s Wide supply voltage range from 0.8 V to 3.6 V
s High noise immunity
s Complies with JEDEC standards:
x JESD8-12 (0.8 V to 1.3 V)
x JESD8-11 (0.9 V to 1.65 V)
x JESD8-7 (1.2 V to 1.95 V)
x JESD8-5 (1.8 V to 2.7 V)
x JESD8-B (2.7 V to 3.6 V)
s ESD protection:
x HBM JESD22-A114-C Class 3A. Exceeds 5000 V
x MM JESD22-A115-A exceeds 200 V
x CDM JESD22-C101-C exceeds 1000 V
s Low static power consumption; ICC = 0.9 µA (maximum)
s Latch-up performance exceeds 100 mA per JESD 78 Class II
s Inputs accept voltages up to 3.6 V
s Low noise overshoot and undershoot < 10 % of VCC
s IOFF circuitry provides partial Power-down mode operation
s Multiple package options
s Specified from −40 °C to +85 °C and −40 °C to +125 °C
1 page Philips Semiconductors
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74AUP1G04
Low-power inverter
Table 7. Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min Typ
II
IOFF
∆IOFF
ICC
input leakage current
power-off leakage current
additional power-off
leakage current
supply current
∆ICC
additional supply current
CI input capacitance
CO output capacitance
Tamb = −40 °C to +85 °C
VIH HIGH-state input voltage
VIL LOW-state input voltage
VOH HIGH-state output voltage
VOL LOW-state output voltage
II
IOFF
∆IOFF
input leakage current
power-off leakage current
additional power-off
leakage current
VI = GND to 3.6 V; VCC = 0 V to 3.6 V
VI or VO = 0 V to 3.6 V; VCC = 0 V
VI or VO = 0 V to 3.6 V;
VCC = 0 V to 0.2 V
VI = GND or VCC; IO = 0 A;
VCC = 0.8 V to 3.6 V
VI = VCC − 0.6 V; IO = 0 A;
VCC = 3.3 V
VCC = 0 V to 3.6 V; VI = GND or VCC
VO = GND; VCC = 0 V
VCC = 0.8 V
VCC = 0.9 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
VCC = 0.8 V
VCC = 0.9 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
VI = VIH or VIL
IO = −20 µA; VCC = 0.8 V to 3.6 V
IO = −1.1 mA; VCC = 1.1 V
IO = −1.7 mA; VCC = 1.4 V
IO = −1.9 mA; VCC = 1.65 V
IO = −2.3 mA; VCC = 2.3 V
IO = −3.1 mA; VCC = 2.3 V
IO = −2.7 mA; VCC = 3.0 V
IO = −4.0 mA; VCC = 3.0 V
VI = VIH or VIL
IO = 20 µA; VCC = 0.8 V to 3.6 V
IO = 1.1 mA; VCC = 1.1 V
IO = 1.7 mA; VCC = 1.4 V
IO = 1.9 mA; VCC = 1.65 V
IO = 2.3 mA; VCC = 2.3 V
IO = 3.1 mA; VCC = 2.3 V
IO = 2.7 mA; VCC = 3.0 V
IO = 4.0 mA; VCC = 3.0 V
VI = GND to 3.6 V; VCC = 0 V to 3.6 V
VI or VO = 0 V to 3.6 V; VCC = 0 V
VI or VO = 0 V to 3.6 V;
VCC = 0 V to 0.2 V
--
--
--
--
--
- 0.8
- 1.7
0.70 × VCC -
0.65 × VCC -
1.6 -
2.0 -
--
--
--
--
VCC − 0.1
0.7 × VCC
1.03
1.30
1.97
1.85
2.67
2.55
-
-
-
-
-
-
-
-
--
--
--
--
--
--
--
--
--
--
--
Max Unit
±0.1 µA
±0.2 µA
±0.2 µA
0.5 µA
40 µA
- pF
- pF
-V
-V
-V
-V
0.30 × VCC V
0.35 × VCC V
0.7 V
0.9 V
-V
-V
-V
-V
-V
-V
-V
-V
0.1
0.3 × VCC
0.37
0.35
0.33
0.45
0.33
0.45
±0.5
±0.5
±0.6
V
V
V
V
V
V
V
V
µA
µA
µA
74AUP1G04_2
Product data sheet
Rev. 02 — 28 June 2006
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
5 of 16
5 Page Philips Semiconductors
www.DataSheet4U.com
74AUP1G04
Low-power inverter
13. Package outline
TSSOP5: plastic thin shrink small outline package; 5 leads; body width 1.25 mm
SOT353-1
D
y
Z
5
4
13
e
e1
bp
wM
EA
X
c
HE
vM A
A2
A1
A
(A3)
Lp
L
detail X
θ
0 1.5 3 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c D(1) E(1) e
mm
1.1
0.1
0
1.0
0.8
0.15
0.30
0.15
0.25
0.08
2.25
1.85
1.35
1.15
0.65
e1
1.3
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
OUTLINE
VERSION
IEC
REFERENCES
JEDEC
JEITA
SOT353-1
MO-203
SC-88A
HE L Lp v w y Z(1) θ
2.25
2.0
0.425
0.46
0.21
0.3
0.1
0.1
0.60
0.15
7°
0°
EUROPEAN
PROJECTION
ISSUE DATE
00-09-01
03-02-19
Fig 9. Package outline SOT353-1 (TSSOP5)
74AUP1G04_2
Product data sheet
Rev. 02 — 28 June 2006
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
11 of 16
11 Page |
Páginas | Total 16 Páginas | |
PDF Descargar | [ Datasheet 74AUP1G04.PDF ] |
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