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PDF STF7N95K3 Data sheet ( Hoja de datos )

Número de pieza STF7N95K3
Descripción Power MOSFET ( Transistor )
Fabricantes STMicroelectronics 
Logotipo STMicroelectronics Logotipo



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STF7N95K3
STP7N95K3, STW7N95K3
N-channel 950 V, 1.1 , 7.2 A, TO-220, TO-220FP, TO-247
Zener-protected SuperMESH3™ Power MOSFET
Features
Type
STF7N95K3
STP7N95K3
STW7N95K3
VDSS
950 V
950 V
950 V
RDS(on)
max
< 1.35
< 1.35
< 1.35
ID Pw
7.2 A 35 W
7.2 A 150 W
7.2 A 150 W
100% avalanche tested
Extremely large avalanche performance
Gate charge minimized
Very low intrinsic capacitances
Zener-protected
Application
Switching applications
Description
The new SuperMESH3™ series is obtained
through the combination of a further fine tuning of
ST's well established strip-based PowerMESH™
layout with a new optimized vertical structure. In
addition to pushing on-resistance significantly
down, special attention has been taken to ensure
a very good dynamic performances coupled with
a very large avalanche capability for the most
demanding application.
3
2
1
TO-247
3
2
1
TO-220
3
2
1
TO-220FP
Figure 1. Internal schematic diagram
Table 1. Device summary
Order codes
STF7N95K3
STP7N95K3
STW7N95K3
Marking
7N95K3
7N95K3
7N95K3
Package
TO-220FP
TO-220
TO-247
Packaging
Tube
Tube
Tube
January 2009
Rev 1
1/15
www.st.com
15

1 page




STF7N95K3 pdf
www.DataSShTeeFt74UN.9co5mK3, STP7N95K3, STW7N95K3
Electrical characteristics
Table 6.
Symbol
Switching times
Parameter
td(on)
tr
td(off)
tf
Turn-on delay time
Rise time
Turn-off-delay time
Fall time
Test conditions
VDD = 475 V, ID = 3.6 A,
RG = 4.7 Ω, VGS = 10 V
(see Figure 19)
Min. Typ. Max Unit
14 ns
9 ns
36 ns
23 ns
Table 7.
Symbol
Source drain diode
Parameter
Test conditions
Min. Typ. Max. Unit
ISD
ISDM (1)
VSD (2)
Source-drain current
Source-drain current (pulsed)
Forward on voltage
ISD = 7.2 A, VGS = 0
trr
Qrr
IRRM
Reverse recovery time
Reverse recovery charge
Reverse recovery current
ISD = 7.2 A, di/dt = 100A/µs
VDD = 60 V (see Figure 24)
trr
Qrr
IRRM
Reverse recovery time
Reverse recovery charge
Reverse recovery current
ISD = 7.2 A, di/dt = 100 A/µs
VDD = 60 V, Tj = 150 °C
(see Figure 24)
1. Pulse width limited by safe operating area
2. Pulsed: Pulse duration = 300 µs, duty cycle 1.5%
7.2 A
28.8 A
1.6 V
450 ns
6 µC
28 A
550 ns
8 µC
28 A
Table 8.
Symbol
Gate-source Zener diode
Parameter
Test conditions
Min. Typ. Max. Unit
BVGSO(1)
Gate-source breakdown
voltage
Igs=± 1mA (open drain)
30
V
1. The built-in back-to-back Zener diodes have specifically been designed to enhance not only the device’s
ESD capability, but also to make them safely absorb possible voltage transients that may occasionally be
applied from gate to source. In this respect the Zener voltage is appropriate to achieve an efficient and
cost-effective intervention to protect the device’s integrity. These integrated Zener diodes thus avoid the
usage of external components
5/15

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STF7N95K3 arduino
www.DataSShTeeFt74UN.9co5mK3, STP7N95K3, STW7N95K3
Package mechanical data
TO-220 mechanical data
mm inch
Dim
Min Typ Max Min Typ Max
A 4.40
4.60
0.173
0.181
b 0.61
0.88
0.024
0.034
b1 1.14
1.70
0.044
0.066
c 0.49
0.70
0.019
0.027
D 15.25
15.75
0.6
0.62
D1 1.27
0.050
E 10
10.40
0.393
0.409
e 2.40
2.70
0.094
0.106
e1 4.95
5.15
0.194
0.202
F 1.23
1.32
0.048
0.051
H1 6.20
6.60
0.244
0.256
J1 2.40
2.72
0.094
0.107
L 13
14 0.511
0.551
L1 3.50
3.93
0.137
0.154
L20 16.40
0.645
L30 28.90
1.137
P 3.75
3.85
0.147
0.151
Q 2.65
2.95
0.104
0.116
11/15

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