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PDF LMX2541 Data sheet ( Hoja de datos )
| Número de pieza | LMX2541 | |
| Descripción | High Performance Frequency Synthesizer System | |
| Fabricantes | National Semiconductor Corporation | |
| Logotipo |  |
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LMX2541
PRELIMINARY
July 2, 2009
Ultra-Low Noise PLLatinum Frequency Synthesizer with
Integrated VCO
General Description
The LMX2541 is an ultra low noise frequency synthesizer
which integrates a high performance delta-sigma fractional N
PLL, a VCO with fully integrated tank circuit, and an optional
frequency divider. The PLL offers an unprecedented normal-
ized noise floor of -225 dBc/Hz and can be operated with up
to 104 MHz of phase-detector rate (comparison frequency) in
both integer and fractional modes. The PLL can also be con-
figured to work with an external VCO.
The LMX2541 integrates several low-noise, high precision
LDOs and output driver matching network to provide higher
supply noise immunity and more consistent performance,
while reducing the number of external components. When
combined with a high quality reference oscillator, the
LMX2541 generates a very stable, ultra low noise signal.
The LMX2541 is offered in a family of 6 devices with varying
VCO frequency range from 1990 MHz up to 4 GHz. Using a
flexible divider, the LMX2541 can generate frequencies as
low as 31.6 MHz. The LMX2541 is a monolithic integrated
circuit, fabricated in a proprietary BiCMOS process. Device
programming is facilitated using a three-wire MICROWIRE
interface that can operate down to 1.8 volts. Supply voltage
ranges from 3.15 to 3.45 volts. The LMX2541 is available in
a 36 pin 6x6x0.8 mm Lead-Free Leadless Leadframe Pack-
age (LLP).
Device
LMX2541SQ2060E
LMX2541SQ2380E
LMX2541SQ2690E
LMX2541SQ3030E
LMX2541SQ3320E
LMX2541SQ3740E
VCO Frequency
1990 - 2240
2200 - 2530
2490 - 2865
2810 - 3230
3130 - 3600
3480 - 4000
Features
■ Very Low RMS Noise and Spurs
— -225 dBc/Hz Normalized PLL Phase Noise
— Integrated RMS Noise (100 Hz - 20 MHz)
■ 2 mrad (100 Hz - 20 MHz) at 2.1 GHz
■ 3.5 mrad (100 Hz - 20 MHz) at 3.5 GHz
■ Ultra Low-Noise Integrated VCO
■ External VCO Option (Internal VCO Bypassed)
■ VCO Frequency Divider 1 to 63 (all values)
■ Programmable Output Power
■ Up to 104 MHz Phase Detector Frequency
■ Integrated Low-Noise LDOs
■ Programmable Charge Pump Output
■ Partially Integrated Loop Filter
■ Digital Frequency Shift Keying (FSK) Modulation Pin
■ Integrated Reference Crystal Oscillator Circuit
■ Hardware and Software Power Down
■ FastLock Mode with Cycle Slip Reduction
■ Analog and Digital Lock Detect
■ 1.6 V Logic Compatibility
Target Applications
■ Wireless Infrastructure (UMTS, LTE, WiMax)
■ Broadband Wireless
■ Wireless Meter Reading
■ Test and Measurement
System Diagram
© 2009 National Semiconductor Corporation 300733
30073322
www.national.com
1 page  
wwAwb.DsatoaSlhueette4UM.coamximum Ratings (Notes 1, 2, 3)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors
for availability and specifications.
Parameter
Power Supply Voltage
Input Voltage to pins other than Vcc Pins
(Note 4)
Storage Temperature
Range
Lead Temperature (solder 4 sec.)
Symbol
Vcc
VIN
TSTG
TL
Ratings
-0.3 to 3.6
-0.3 to (Vcc+0.3)
-65 to 150
+ 260
Units
V
VIN
°C
°C
Recommended Operating Conditions
Parameter
Power Supply Voltage
(All Vcc Pins)
Ambient Temperature
Symbol
Vcc
TA
Min
3.15
-40
Typ
3.3
Max Units
3.45 V
+85 °C
Note 1: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device
is intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics.
The guaranteed specifications apply only to for the test conditions listed.
Note 2: This Device is a high performance RF integrated circuit with an ESD rating < 2kV and is ESD sensitive. Handling and assembly of this device should only
be done at ESD-free workstations.
Note 3: Stresses in excess of the absolute maximum ratings can cause permanent or latent damage to the device. These are absolute stress ratings only.
Functional operation of the device is only implied at these or any other conditions in excess of those given in the
Note 4: Never to exceed 3.6 V.
5 www.national.com
5 Page 
wwSwe.DraitaaSlhDeeta4Uta.coTm iming Diagram
30073303
The DATA is clocked into a shift register on each rising edge of the CLK signal. On the rising edge of the LE signal, the data is
sent from the shift registers to an actual counter. A slew rate of at least 30 V/μs is recommended for these signals. After the
programming is complete, the CLK, DATA, and LE signals should be returned to a low state. If the CLK and DATA lines are toggled
while the in VCO is in lock , as is sometimes the case when these lines are shared with other parts, the phase noise may be
degraded during the time of this programming.
11 www.national.com
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet LMX2541.PDF ] | |
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