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PDF LMK03002C Data sheet ( Hoja de datos )

Número de pieza LMK03002C
Descripción Precision Clock Conditioner
Fabricantes National Semiconductor 
Logotipo National Semiconductor Logotipo



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No Preview Available ! LMK03002C Hoja de datos, Descripción, Manual

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August 2007
LMK03002/LMK03002C
Precision Clock Conditioner with Integrated VCO
General Description
The LMK03002/LMK03002C precision clock conditioners
combine the functions of jitter cleaning/reconditioning, multi-
plication, and distribution of a reference clock. The devices
integrate a Voltage Controlled Oscillator (VCO), a high per-
formance Integer-N Phase Locked Loop (PLL), a partially
integrated loop filter, and four LVPECL clock output distribu-
tion blocks.
The VCO output is optionally accessible on the Fout port. In-
ternally, the VCO output goes through a VCO Divider to feed
the various clock distribution blocks.
Each clock distribution block includes a programmable di-
vider, a phase synchronization circuit, a programmable delay,
a clock output mux, and an LVPECL output buffer. This allows
multiple integer-related and phase-adjusted copies of the ref-
erence to be distributed to four system components.
The clock conditioners come in a 48-pin LLP package and are
footprint compatible with other clocking devices in the same
family.
Features
Integrated VCO with very low phase noise floor
Integrated Integer-N PLL with outstanding normalized
phase noise contribution of -224 dBc/Hz
Clock generator performance (10 Hz - 20 MHz)
LMK03002C: 200 fs RMS jitter
Jitter cleaner performance grade (12 kHz to 20 MHz)
LMK03002: 800 fs RMS jitter
LMK03002C: 400 fs RMS jitter
VCO frequency: 1566 to 1724 MHz
Clock output frequency range of 1 to 862 MHz
4 LVPECL clock outputs
Partially integrated loop filter
Dedicated divider and delay blocks on each clock output
Pin compatible family of clocking devices
3.15 to 3.45 V operation
Package: 48 pin LLP (7.0 x 7.0 x 0.8 mm)
Target Applications
Data Converter Clocking
Networking, SONET/SDH, DSLAM
Wireless Infrastructure
Medical
Test and Measurement
Military / Aerospace
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 2007 National Semiconductor Corporation 300206
www.national.com

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LMK03002C pdf
Symbol
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Parameter
Conditions
PLL (Continued)
ISINKCPout Charge Pump Sink Current
ICPoutTRI
ICPout%MIS
Charge Pump TRI-STATE® Current
Magnitude of Charge Pump
Sink vs. Source Current Mismatch
Magnitude of Charge Pump
ICPoutVTUNE Current vs. Charge Pump Voltage
Variation
VCPout = Vcc/2, PLL_CP_GAIN = 1x
VCPout = Vcc/2, PLL_CP_GAIN = 4x
VCPout = Vcc/2, PLL_CP_GAIN = 16x
VCPout = Vcc/2, PLL_CP_GAIN = 32x
0.5 V < VCPout < Vcc - 0.5 V
VCPout = Vcc / 2
TA = 25°C
0.5 V < VCPout < Vcc - 0.5 V
TA = 25°C
ICPoutTEMP
Magnitude of Charge Pump Current vs.
Temperature Variation
PN10kHz
PLL 1/f Noise at 10 kHz Offset (Note 6) PLL_CP_GAIN = 1x
Normalized to 1 GHz Output Frequency PLL_CP_GAIN = 32x
PN1Hz
Normalized Phase Noise Contribution
(Note 7)
PLL_CP_GAIN = 1x
PLL_CP_GAIN = 32x
VCO
fFout
TCL|
VCO Tuning Range
Allowable Temperature Drift for
Continuous Lock
LMK03002/LMK03002C
After programming R15 for lock, no
changes to output configuration are
permitted to guarantee continuous
lock. (Note 8)
pFout
KVtune
Output Power to a 50 load driven by Fout LMK03002/LMK03002C; TA = 25 °C
Fine Tuning Sensitivity
(The lower sensitivity indicates the typical
sensitivity at the lower end of the tuning LMK03002/LMK03002C
range, the higher sensitivity at the higher
end of the tuning range)
JRMSFout Fout RMS Period Jitter
LMK03002
12 kHz to 20 MHz bandwidth
LMK03002C
12 kHz to 20 MHz bandwidth
L(f)Fout
Fout Single Side Band Phase Noise
LMK03002C
fFout = 1724 MHz
(Note 9)
LMK03002C
fFout = 1566 MHz
(Note 9)
10 kHz Offset
100 kHz Offset
1 MHz Offset
10 MHz Offset
10 kHz Offset
100 kHz Offset
1 MHz Offset
10 MHz Offset
Min Typ Max Units
-100
-400
-1600
-3200
2
3
10
μA
nA
%
4%
4
-117
-122
-219
-224
%
dBc/Hz
dBc/Hz
1566
1724 MHz
125 °C
2 dBm
11 to 15
MHz/V
800
400
-89
-113
-135
-155
-91
-115
-137
-156
fs
dBc/Hz
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