PDF LMK01010 Data sheet ( Hoja de datos )

Número de pieza	LMK01010
Descripción	(LMK01000 - LMK01020) 1.6 GHz High Performance Clock Buffer
Fabricantes	National Semiconductor
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No Preview Available ! www.DataSheet4U.com March 6, 2008 LMK01000/LMK01010/LMK01020 1.6 GHz High Performance Clock Buffer, Divider, and Distributor General Description The LMK01000/LMK01010/LMK01020 family provides an easy way to divide and distribute high performance clock sig- nals throughout the system. These devices provide best-in- class noise performance and are designed to be pin-to-pin and footprint compatible with LMK03000/LMK02000 family of precision clock conditioners. The LMK01000/LMK01010/LMK01020 family features two programmable clock inputs (CLKin0 and CLKin1) that allow the user to dynamically switch between different clock do- mains. Each device features 8 clock outputs with independently pro- grammable dividers and delay adjustments. The outputs of the device can be easily synchronized by an external pin (SYNC*). Target Applications ■ High performance Clock Distribution ■ Wireless Infrastructure ■ Medical Imaging ■ Wired Communications ■ Test and Measurement ■ Military / Aerospace Features ■ 30 fs additive jitter (100 Hz to 20 MHz) ■ Dual clock inputs ■ Programmable output channels (0 to 1600 MHz) — LMK01000: 3 LVDS outputs (CLKout0 - CLKout2) + 5 LVPECL outputs (CLKout3 - CLKout7) — LMK01010: 8 LVDS outputs — LMK01020: 8 LVPECL outputs — Channel divider values of 1, 2 to 510 (even divides) — Programmable output skew control ■ External synchronization ■ Pin compatible family of clocking devices ■ 3.15 to 3.45 V operation ■ Package: 48 pin LLP (7.0 x 7.0 x 0.8 mm) System Diagram TRI-STATE® is a registered trademark of National Semiconductor Corporation. © 2008 National Semiconductor Corporation 300428 30042806 www.national.com 1 page Symbol www.DataSheet4U.com Parameter Conditions Clock Distribution Section--Delays DelayCLKout Maximum Allowable Delay(Note 8) fCLKoutX ≤ 1 GHz (Delay is limited to maximum programmable value) fCLKoutX > 1 GHz (Delay is limited to 1/2 of a period) Clock Distribution Section - Divides DivideCLKoutX Allowable divide range. (Note that 1 is fCLKinX ≤ 1300 MHz the only allowable odd divide value) 1300 MHz < fCLKinX ≤ 1600 MHz Clock Distribution Section - LVDS Clock Outputs JitterADD Additive RMS Jitter (Note 7) RL = 100 Ω fCLKoutX = 200 MHz Bandwidth = fCLKoutX = 800 MHz 100 Hz to 20 MHz Vboost = 1 fCLKoutX = 1600 MHz Noise Floor Divider Noise Floor(Note 7) tSKEW VOD CLKoutX to CLKoutY (Note 8) Differential Output Voltage RL = 100 Vboost = 1 fCLKoutX = 200 MHz fCLKoutX = 800 MHz fCLKoutX = 1600 MHz Equal loading and identical clock configuration RL = 100 Ω (Note 9) Vboost=0 Vboost=1 ΔVOD Change in magnitude of VOD for complementary output states RL = 100 Ω VOS ΔVOS Output Offset Voltage Change in magnitude of VOS for complementary output states RL = 100 Ω RL = 100 Ω ISA ISB Clock Output Short Circuit Current single ended Single ended outputs shorted to GND ISAB Clock Output Short Circuit Current differential Complementary outputs tied together Min 1 1 -30 250 -50 1.070 -35 -24 -12 Typ Max Units 2250 0.5/ fCLKoutX ps 510 n/a 2 80 30 25 -156 -153 -148 fs dBc/Hz ±4 30 ps 350 450 390 50 1.25 1.370 35 mV mV V mV 24 mA 12 mA 5 www.national.com 5 Page www.DataSheet4U.com CLKout0 CLKout1 CLKout2 CLKout3 CLKout4 CLKout5 CLKout6 CLKout7 _EN _EN _EN _EN _EN _EN _EN _EN RESET POWERDOWN EN_CLKout _Global CLKin _SELECT 11 www.national.com 11 Page

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