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PDF ADCLK950 Data sheet ( Hoja de datos )
| Número de pieza | ADCLK950 | |
| Descripción | SiGe Clock Fanout Buffer | |
| Fabricantes | Analog Devices | |
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Data Sheet
Two Selectable Inputs, 10 LVPECL Outputs,
SiGe Clock Fanout Buffer
ADCLK950
FEATURES
2 selectable differential inputs
4.8 GHz operating frequency
75 fs rms broadband random jitter
On-chip input terminations
3.3 V power supply
APPLICATIONS
Low jitter clock distribution
Clock and data signal restoration
Level translation
Wireless communications
Wired communications
Medical and industrial imaging
ATE and high performance instrumentation
GENERAL DESCRIPTION
The ADCLK950 is an ultrafast clock fanout buffer fabricated
on the Analog Devices, Inc., proprietary XFCB3 silicon germanium
(SiGe) bipolar process. This device is designed for high speed
applications requiring low jitter.
The device has two selectable differential inputs via the IN_SEL
control pin. Both inputs are equipped with center tapped,
differential, 100 Ω on-chip termination resistors. The inputs
accept dc-coupled LVPECL, CML, 3.3 V CMOS (single-ended),
and ac-coupled 1.8 V CMOS, LVDS, and LVPECL inputs. A
VREFx pin is available for biasing ac-coupled inputs.
The ADCLK950 features 10 full-swing emitter coupled logic
(ECL) output drivers. For LVPECL (positive ECL) operation,
bias VCC to the positive supply and VEE to ground. For ECL
operation, bias VCC to ground and VEE to the negative supply.
The output stages are designed to directly drive 800 mV each
side into 50 Ω terminated to VCC − 2 V for a total differential
output swing of 1.6 V.
The ADCLK950 is available in a 40-lead LFCSP and specified
for operation over the standard industrial temperature range of
−40°C to +85°C.
FUNCTIONAL BLOCK DIAGRAM
ADCLK950
LVPECL
Q0
Q0
Q1
Q1
Q2
Q2
VREF0
REFERENCE
Q3
Q3
VT0
CLK0
CLK0
VT1
CLK1
CLK1
Q4
Q4
Q5
Q5
Q6
Q6
IN_SEL
Q7
Q7
VREF1
REFERENCE
Q8
Q8
Q9
Q9
Figure 1.
Rev. B
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2009–2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
ADCLK950
Table 3. Input Select Control Pin
Parameter
Logic 1 Voltage
Logic 0 Voltage
Logic 1 Current
Logic 0 Current
Capacitance
Symbol
VIH
VIL
IIH
IIL
Min
VCC − 0.4
VEE
Data Sheet
Typ Max
VCC
1
100
0.6
2
Unit
V
V
μA
mA
pF
Table 4. Power
Parameter
POWER SUPPLY
Supply Voltage Requirement
Power Supply Current
Negative Supply Current
Positive Supply Current
Power Supply Rejection1
Output Swing Supply Rejection2
Symbol Min Typ Max Unit Test Conditions/Comments
VCC − VEE 2.97
IVEE
IVCC
PSRVCC
PSRVCC
106
346
<3
28
3.63 V 3.3 V + 10%
Static
130 mA VCC − VEE = 3.3 V ± 10%
390 mA VCC − VEE = 3.3 V ± 10%
ps/V
VCC − VEE = 3.3 V ± 10%
dB VCC − VEE = 3.3 V ± 10%
1 Change in tPD per change in VCC.
2 Change in output swing per change in VCC.
Rev. B | Page 4 of 12
5 Page 
ADCLK950
CLOCK INPUT SELECT (IN_SEL) SETTINGS
A Logic 0 on the IN_SEL pin selects the Input CLK0 and
Input CLK0. A Logic 1 on the IN_SEL pin selects Input CLK1
and Input CLK1.
PCB LAYOUT CONSIDERATIONS
The ADCLK950 buffer is designed for very high speed applica-
tions. Consequently, high speed design techniques must be used
to achieve the specified performance. It is critically important
to use low impedance supply planes for both the negative supply
(VEE) and the positive supply (VCC) planes as part of a multilayer
board. Providing the lowest inductance return path for switching
currents ensures the best possible performance in the target
application.
The following references to the GND plane assume that the VEE
power plane is grounded for LVPECL operation. Note that for
ECL operation, the VCC power plane becomes the ground plane.
It is also important to adequately bypass the input and output
supplies. Place a 1 µF electrolytic bypass capacitor within several
inches of each VCC power supply pin to the GND plane. In
addition, place multiple high quality 0.001 µF bypass capacitors
as close as possible to each of the VCC supply pins, and connect
the capacitors to the GND plane with redundant vias. Carefully
select high frequency bypass capacitors for minimum induc-
tance and ESR. To improve the effectiveness of the bypass at
high frequencies, minimize parasitic layout inductance. Also,
avoid discontinuities along input and output transmission lines
that can affect jitter performance.
In a 50 Ω environment, input and output matching have a
significant impact on performance. The buffer provides internal
50 Ω termination resistors for both CLKx and CLKx inputs.
Normally, the return side is connected to the reference pin that is
provided. Carefully bypass the termination potential using
ceramic capacitors to prevent undesired aberrations on the
input signal due to parasitic inductance in the termination
Data Sheet
return path. If the inputs are dc-coupled to a source, take care to
ensure that the pins are within the rated input differential and
common-mode ranges.
If the return is floated, the device exhibits a 100 Ω cross termi-
nation, but the source must then control the common-mode
voltage and supply the input bias currents.
There are ESD/clamp diodes between the input pins to prevent
the application from developing excessive offsets to the input
transistors. ESD diodes are not optimized for best ac perfor-
mance. When a clamp is required, it is recommended that
appropriate external diodes be used.
Exposed Metal Paddle
The exposed metal paddle on the ADCLK950 package is both
an electrical connection and a thermal enhancement. For the
device to function properly, the paddle must be properly
attached to the VEE power plane.
When properly mounted, the ADCLK950 also dissipates heat
through its exposed paddle. The PCB acts as a heat sink for the
ADCLK950. The PCB attachment must provide a good thermal
path to a larger heat dissipation area. This requires a grid of vias
from the top layer down to the VEE power plane (see Figure 18).
The ADCLK950 evaluation board (ADCLK950/PCBZ) provides
an example of how to attach the part to the PCB.
VIAS TO VEE POWER
PLANE
Figure 18. PCB Land for Attaching Exposed Paddle
Rev. B | Page 10 of 12
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet ADCLK950.PDF ] | |
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