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PDF ISL59920 Data sheet ( Hoja de datos )

Número de pieza ISL59920
Descripción Triple Analog Video Delay Line
Fabricantes Intersil Corporation 
Logotipo Intersil Corporation Logotipo



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®
Data Sheet
December 19, 2008
ISL59920
FN6826.0
Triple Analog Video Delay Line
The ISL59920 ia a triple analog delay line that provides skew
compensation between three high-speed signals. These
parts are ideal for compensating for the skew introduced by
a typical CAT-5 cable (with differing electrical lengths on
each twisted pair) when transmitting analog video.
Using a simple serial interface, the ISL59920’s delay is
programmable in steps of 2ns up to a total delay of 62ns on
each channel. The gain of the video amplifiers can be set to
x1 (0dB) or x2 (6dB) for back-termination. The delay lines
require a ±5V supply.
Pinout
ISL59920
(20 LD 5X5 QFN)
TOP VIEW
Features
• 62ns total delay
• 2.0ns delay step increments
• Very low offset voltage
• Drop-in compatible with the EL9115
• Low power consumption
• Pb-free RoHS compliant 20 Ld QFN package
Applications
• Skew control for RGB video signals
• Generating programmable high-speed analog delays
VSP 1
RIN 2
GND 3
GIN 4
VSM 5
THERMAL
PAD
15 ROUT
14 GNDO
13 GOUT
12 VSMO
11 BOUT
Ordering Information
PART
NUMBER
PART
MARKING
DELAY STEP
SIZE
TYPICAL POWER
MAX DELAY (ns)
(ns)
DISSIPATION
PACKAGE
PKG.
DWG. #
ISL59920IRZ
59920IRZ
62
2.0
645mW
20 Ld 5mm x 5mm QFN
L20.5x5C
ISL59920IRZ-T7*
59920IRZ
62
2.0
645mW
20 Ld 5mm x 5mm QFN
L20.5x5C
*Please refer to TB347 for details on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100%
matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations).
Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J
STD-020.
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2008. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.

1 page




ISL59920 pdf
ISL59920
www.TDaytapSihceaetl4UP.ceormformance Curves
2
1
0
-1
-2
-3
-4
-5
-6
-7
-8 VIN = 700mVP-P
-9 GAIN = 1
-10
100k
1M
0ns
10ns
30ns
50ns
10M
FREQUENCY (Hz)
100M
20ns
40ns
62ns
1G
FIGURE 2. FREQUENCY RESPONSE (GAIN = 1)
2
1
0
-1
-2
-3
-4
-5
-6
-7
-8 VIN = 700mVP-P
-9 GAIN = 2
-10
100k
1M
0ns
10ns
30ns
50ns
10M
FREQUENCY (Hz)
100M
20ns
40ns
62ns
1G
FIGURE 3. FREQUENCY RESPONSE (GAIN = 2)
SENABLE
TIMEBASE: 500ns/div
SENABLE: 1V/div
OUTPUT: 100mV/div
GAIN: 1
OUTPUT
FIGURE 4. OFFSET CORRECTION DAC ADJUST
250
200
150
100
50
0
0
100M
200M
300M
400M
500M
FREQUENCY (Hz)
FIGURE 5. NOISE SPECTRUM (10k TO 500MHz)
3.0
2.5 RISE
2.0
1.5 FALL
1.0
0.5
0
0 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60
DELAY (ns)
FIGURE 6. RISE/FALL TIME vs DELAY TIME (GAIN = 1)
3.0
2.5 RISE
2.0
1.5 FALL
1.0
0.5
0
0 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60
DELAY (ns)
FIGURE 7. RISE/FALL TIME vs DELAY TIME (GAIN = 2)
5 FN6826.0
December 19, 2008

5 Page





ISL59920 arduino
ISL59920
www.QDautaaShdeeFt4lUa.ctoNm o-Lead Plastic Package (QFN)
A DB
1
2
3
(2X)
0.075 C
PIN #1
I.D. MARK
E
TOP VIEW
e
C
0.10 C
SEATING
PLANE
0.08 C
N LEADS AND
EXPOSED PAD
SEE DETAIL “X”
SIDE VIEW
L
N LEADS
(E2)
0.01 M C A B
b
PIN #1 I.D.
3
1
2
3
NE 5
(D2)
BOTTOM VIEW
7
L20.5x5C
20 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
(COMPLIANT TO JEDEC MO-220)
SYMBOL
A
A1
b
c
D
D2
E
E2
e
L
MILLIMETERS
MIN NOMINAL MAX
0.80 0.90 1.00
0.00 0.02 0.05
0.28 0.30 0.32
0.20 REF
5.00 BASIC
3.70 REF
5.00 BASIC
3.70 REF
0.65 BASIC
0.35 0.40 0.45
NOTES
-
-
-
-
-
8
-
8
-
-
N 20 4
ND 5 REF 6
NE 5 REF 5
Rev. 0 6/06
NOTES:
1. Dimensioning and tolerancing per ASME Y14.5M-1994.
2. Tiebar view shown is a non-functional feature.
3. Bottom-side pin #1 I.D. is a diepad chamfer as shown.
4. N is the total number of terminals on the device.
5. NE is the number of terminals on the “E” side of the package
(or Y-direction).
6. ND is the number of terminals on the “D” side of the package
(or X-direction). ND = (N/2)-NE.
7. Inward end of terminal may be square or circular in shape with
radius (b/2) as shown.
8. If two values are listed, multiple exposed pad options are
available. Refer to device-specific datasheet.
9. One of 10 packages in MDP0046
C A (c)
A1
DETAIL “X”
2
(L)
N LEADS
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
11 FN6826.0
December 19, 2008

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