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PDF HT82A6216 Data sheet ( Hoja de datos )
| Número de pieza | HT82A6216 | |
| Descripción | A/D Type Full Speed USB 8-Bit MCU | |
| Fabricantes | Holtek Semiconductor | |
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HT82A623R/HT82A6208/HT82A6216
A/D Type Full Speed USB 8-Bit MCU with SPI
Technical Document
· Application Note
- HA0075E MCU Reset and Oscillator Circuits Application Note
Features
· Operating voltage:
fSYS = 6MHz: 2.2V~5.5V
fSYS = 12MHz: 3.0V~5.5V
· 4K´15 Program Memory
· 160´8 data memory RAM
· HT82A6208: 8M´1 bits Flash memory structure
· HT82A6216: 16M´1 bits or 8Mx2 bits Flash memory
structure
· 32 bidirectional I/O lines
· USB 2.0 Full Speed Compatible
· One external interrupt input shared with I/O line
· Two 16-bit programmable Timer/Event Counters
with overflow interrupt
· Two SPI interfaces (master and slave mode) shared
with PA0~PA3, PB0~PB3
· Total of 6 Interrupts - EXT, Timer0, Timer1, SPIA,
SPIB, USB
· Flash Serial Peripheral Interface compatible - Mode0
and Mode3
· 8288608´1bit Flash memory structure - HT82A6208
· 16777216´1bit or 8388608x2bit Flash memory
structure - HT82A6216
· 256 Equal Sector with 4K byte each for Flash
memory structure- HT82A6208
· 512 Equal Sector with 4K byte each for Flash
memory structure- HT82A6216
· Flash Memory Input Data Format: 1-byte Command
code
· Flash Memory Block Lock protection
· Single Power Supply Operation
· Watchdog Timer function
· 32768Hz Real time clock
· Power down and wake-up functions to reduce power
consumption
· 16 channel 12-bit resolution A/D converter
· 2-channel 8-bit PWM output shared with two I/O
lines
· Up to 0.33ms instruction cycle with 12MHz system
clock at VDD=5V
· Max. 4 endpoints supported - endpoint 0 included
· All endpoints support Interrupt, & bulk transfer
· Endpoint 0 supports control, interrupt and bulk
transfer
· All endpoints except endpoint 0 can be configured
as 8, 16, 32, 64 FIFO size
· Endpoint 0 has 8 byte FIFO
· Total FIFO size: 64+8 bytes (RAM0: 48 bytes;
RAM1:16 bytes, 8 bytes for endpoint0)
· 2.2V ± 5% LVD
· 6-level subroutine nesting
· Bit manipulation instruction
· Table read instructions
· 63 powerful instructions
· All instructions executed in one or two machine
cycles
· Low voltage reset function
· Wide range of available package types
Rev. 1.00
1 July 3, 2009
1 page  
www.DataSheet4U.com
HT82A623R/HT82A6208/HT82A6216
Pin Description
Pin Name
PA0/CSA
PA1/SCLKA
PA2/SDIA
PA3/SDOA
PA4/PWM0
PA5/PWM1
PA6/INT
PA7/TMR0
PB0/AN0/CSB
PB1/AN1/SCLKB
PB2/AN2/SDIB
PB3/AN3/SDOB
PB4/AN4
PB5/AN5
PB6/AN6
PB7/AN7/VDDIO
PC0/AN8~
PC7/AN15
PD0/TMR1
PD1~PD7
I/O Options
Description
Bidirectional 8-bit input/output port. Each pin can be configured as a
Pull-high wake-up input by a configuration option. Software instructions determine if
I/O
Wake-up
NMOS or
the pin is a CMOS output or Schmitt Trigger input. Configuration options
determine if the pins have pull-high resistors. The INTB and TMR0 pins are
CMOS pin-shared with PA6 and PA7 respectively. PA0~PA3 are shared with the
SPIA function. PA4~PA5 are shared with PWM0 and PWM1.
Bidirectional 8-bit input/output port. Each nibble, PB0~PB3 and PB4~PB7
pin can be configured as a wake-up input by a configuration option. Soft-
I/O
Pull-high
Wake-up
PB7/VDDIO
PB0~PB6
with VDDIO
ware instructions determine if the pin is a CMOS output or Schmitt Trigger
input. Configuration options determine if the pins have pull-high resistors.
PB is pin shared with the A/D inputs. Once a PB line is selected as an A/D
input using software control, the I/O function and pull-high resistor are dis-
abled automatically. PB7 can be configured as a normal I/O or a VDDIO pin
by configuration option. The power supply for pins PB0~PB6 can be set to
either VDD or VDDIO by configuration options. PB0~PB3 are shared with
SPIB.
Bidirectional 8-bit input/output port. Each nibble, PC0~PC3 and PC4~PC7
pin can be configured as a wake-up input by a configuration option. Soft-
I/O
Pull-high
Wake-up
ware instructions determine if the pin is a CMOS output or Schmitt Trigger
input. Configuration options determine if the pins have pull-high resistors.
PC is pin shared with the A/D inputs. Once a PC line is selected as an A/D
input using software control, the I/O function and pull-high resistor are dis-
abled automatically.
Bi-directional 8-bit input/output port. Each nibble, PD0~PD3 and PD4~PD7
I/O
Pull-high
Wake-up
pin can be configured as a wake-up input by a configuration option. Soft-
ware instructions determine if the pin is a CMOS output or Schmitt Trigger
input. Configuration options determine if the pins have pull-high resistors.
The TMR1 pin is shared with PD0.
D-/DATA
D+/CLK
V33O
I/O ¾ USBD- line
I/O ¾ USBD+ line
O ¾ 3.3V regulator output
UBUS
OSCI
OSCO
¾ ¾ USB SIE VDD
I
O
¾
OSCI, OSCO are connected to an external 6MHz or 12MHz Crystal/reso-
nator, determined by software instructions, for the internal system clock
RES
I ¾ Schmitt trigger reset input. Active low
VDD
¾ ¾ Positive power supply of IC except for USBSIE
CS#, PADCS#
I
¾ Flash Memory chip select
SI, PADSI
I ¾ Flash Memory Serial data input
SO, PADSO
O ¾ Flash Memory Serial data output
SCLK, PADSCLK I
HOLD, PADHOLD I
WP, PADWP
I
VCC
¾
¾ Flash Memory Clock input
¾ Flash Memory Hold, to pause the device without deselecting the device
¾ Flash Memory Write protection
¾ 3.3V power supply
Note: The Pin Description reflects the situation of the largest package, smaller package types may not contain all
pins described in the table.
Rev. 1.00
5 July 3, 2009
5 Page 
www.DataSheet4U.com
HT82A623R/HT82A6208/HT82A6216
· Location 018H
This vector is used by the timer1 counter. If a counter
overflow occurs, the program will jump to this location
and begin execution if the timer interrupt is enabled
and the stack is not full.
Look-up Table
Any location within the Program Memory can be defined
as a look-up table where programmers can store fixed
data. To use the look-up table, one method is to first
setup a low byte table pointer by placing the lower order
address of the look up data to be retrieved in the low
byte table pointer register, TBLP. This register defines
the lower 8-bit address of the look-up table.
After setting up the table pointer, the table data can be
retrieved from the current Program Memory page or last
Program Memory page using the ²TABRDC[m]² or
²TABRDL [m]² instructions, respectively. When these in-
structions are executed, the lower order table byte from
the Program Memory will be transferred to the user de-
fined Data Memory register [m] as specified in the in-
struction. The higher order table data byte from the
Program Memory will be transferred to the TBLH special
register. Any unused bits in this transferred higher order
byte will be read as ²0².
The following diagram illustrates the addressing/data
flow of the look-up table:
P ro g ra m C o u n te r
H ig h B y te
TB LP
P ro g ra m
M e m o ry
TB LH
T a b le C o n te n ts H ig h B y te
S p e c ifie d b y [m ]
T a b le C o n te n ts L o w B y te
Table Read - TBLP only
TBH P
TB LP
P ro g ra m
M e m o ry
TB LH
H ig h B y te o f T a b le C o n te n ts
S p e c ifie d b y [m ]
L o w B y te o f T a b le C o n te n ts
Table Read - TBLP/TBHP
Table Program Example
Another method is to setup the full table address using
both the TBLP and TBHP low and high byte table pointer
registers to directly address any area in he Program
Memory. In this way any page of data can be accessed
directly using the TABRDL instruction. If the TBHP high
byte table pointer register is to be used, then it must first
be enabled with a configuration option.
The following example shows how the table pointer and
table data is defined and retrieved from the
microcontroller. This example uses raw table data lo-
cated in the last page which is stored there using the
ORG statement. The value at this ORG statement is
²F00H² which refers to the start address of the last page
within the 4K Program Memory of device. The table
pointer is setup here to have an initial value of ²06H².
This will ensure that the first data read from the data ta-
ble will be at the Program Memory address ²F06H² or 6
locations after the start of the last page. Note that the
value for the table pointer is referenced to the first ad-
dress of the present page if the ²TABRDC [m]² instruc-
tion is being used. The high byte of the table data which
in this case is equal to zero will be transferred to the
TBLH register automatically when the ²TABRDL [m]² in-
struction is executed.
Table Location Bits
Instruction
b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
TABRDC [m] PC11 PC10 PC9 PC8 @7 @6 @5 @4 @3 @2 @1 @0
TABRDL [m] 1 1 1 1 @7 @6 @5 @4 @3 @2 @1 @0
Table Location
Note: PC11~PC8: Current Program Counter bits
@7~@0: Table Pointer TBLP bits
TBHP register bit3~bit0 when TBHP is enabled
Rev. 1.00
11 July 3, 2009
11 Page | ||
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| PDF Descargar | [ Datasheet HT82A6216.PDF ] | |
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