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PDF CYM1465A Data sheet ( Hoja de datos )
| Número de pieza | CYM1465A | |
| Descripción | 512K x 8 PDIP Static RAM | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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CYM1465A
Features
• 4.5V–5.5V operation
• CMOS SRAM for optimum speed and power
• Low active power (165 mW max.)
• Low standby power (L Version)—(110 µW max)
• 2V data retention (L Version)
• JEDEC-compatible pinout
• 32-pin, 0.6-inch-wide DIP package
• TTL-compatible inputs and outputs
Functional Description
The CYM1465A is a high-performance CMOS static RAM or-
ganized as 512K words by 8 bits. Easy memory expansion is
provided by an active LOW chip enable (CE), an active LOW
Output Enable (OE), and three-state drivers. This device has
512K x 8 PDIP Static RAM
an automatic power-down feature that reduces power con-
sumption by more than 99% when deselected.
Writing to the SRAM is accomplished when the chip select
(CS) and write enable (WE) inputs are both LOW. Data on the
eight input/output pins (I/O0 through I/O7) of the device is then
written into the memory location specified on the address pins
(A0 through A18). Reading from the device is accomplished by
taking chip select (CE) and output enable (OE) LOW while
write enable (WE) remains inactive or HIGH. Under these con-
ditions, the contents of the memory location specified on the
address pins (A0 through A18) will appear on the eight appro-
priate data input/output pins (I/O0 through I/O7).The eight in-
put/output pins (I/O0 through I/O7) are placed in a high imped-
ance state when the device is deselected (CE HIGH), the
outputs are disabled (OE HIGH), or during a write operation
(CE LOW, and WE LOW).
The CYM1465A is available in a 32-pin 600-mil wide body
PDIP package.
Logic Block Diagram
A0
A1
A4
A5
A6
A7
A12
A14
A16
A17
CE
WE
OE
INPUT BUFFER
512 x 256 x 8
ARRAY
COLUMN
DECODER
POWER
DOWN
Selection Guide
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum Standby Current (µA)
Pin Configuration
DIP
Top View
A18 1 S
32 VCC
A16 2
A14 3
31 A15
30 A17
A12 4
29 WE
I/O0
A7 5
28 A13
A6 6
27 A8
I/O1
A5 7
A4 8
26 A9
25 A11
I/O2
A3 9
A2 10
24 OE
23 A10
I/O3
A1 11
A0 12
22 CE
21 I/O7
I/O4
I/O0
I/O1
13
14
20 I/O6
19 I/O5
I/O5
I/O2 15
18 I/O4
GND 16
17 I/O3
I/O6
I/O7
CYM1465A-70
70
20
20
CYM1465A-85
85
20
20
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-05269 Rev. **
Revised March 15, 2002
1 page  
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Switching Waveforms (continued)
Write Cycle No. 1 (WE Controlled) [4]
ADDRESS
CE
tSA
WE
tWC
tSCE
tAW
tPWE
tHA
DATA IN
DATAOUT
DATA UNDEFINED
tSD
DATA VALID
tHD
tHZWE
tLZWE
HIGH IMPEDANCE
CYM1465A
[4,9]
Write Cycle No. 2 (CE Controlled)
ADDRESS
CE
tSA
WE
tWC
tAW
DATA IN
DATA OUT
DATA UNDEFINED
tSCE
tPWE
tHA
tSD tHD
DATA VALID
tHZWE
HIGH IMPEDANCE
Note:
9. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
Truth Table
Inputs
CE WE OE
HXX
LHL
LLX
L HH
Output
High Z
Data Out
Data In
High Z
Mode
Deselect/Power-Down
Read Word
Write Word
Deselect
Document #: 38-05269 Rev. **
Page 5 of 7
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet CYM1465A.PDF ] | |
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