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PDF DS8023 Data sheet ( Hoja de datos )
| Número de pieza | DS8023 | |
| Descripción | Smart Card Interface | |
| Fabricantes | Maxim Integrated Products | |
| Logotipo |  |
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Rev 0; 8/08
www.DataSheet4U.com
Smart Card Interface
General Description
The DS8023 smart card interface IC is a low-cost, low-
power, analog front-end for a smart card reader designed
for all ISO 7816, EMV*, and GSM11-11 applications. The
DS8023 supports 5V, 3V, and 1.8V smart cards, and pro-
vides an option for ultra-low stop-mode power consump-
tion. The DS8023 is available in 28-pin TSSOP and SO
packages, and can often be used as a replacement for
the TDA8024 with little or no application changes.
The DS8023 is designed to interface between a system
microcontroller and the smart card interface, providing
all power supply, protection, and level shifting required
for IC card applications.
Applications
Set-Top Box Conditional Access
Access Control
Banking Applications
POS Terminals
Debit/Credit Payment Terminals
PIN Pads
Automated Teller Machines
Telecommunications
Pay/Premium Television
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
DS8023-RJX+
-40°C to +85°C
28 TSSOP
DS8023-RRX+
-40°C to +85°C
28 SO
Note: Contact the factory for availability of other variants and
package options.
+Denotes a lead-free/RoHS-compliant package.
Selector Guide appears at end of data sheet.
Features
♦ Analog Interface and Level Shifting for IC Card
Communication
♦ ±8kV (min) ESD (IEC) Protection on Card Interface
Pins
♦ Ultra-Low Stop-Mode Current, Less Than 10nA (typ)
♦ Internal IC Card-Supply Voltage Generation
5.0V ±5%, 80mA (max)
3.0V ±8%, 65mA (max)
1.8V ±10%, 30mA (max)
♦ Automatic Card Activation and Deactivation
Controlled by Dedicated Internal Sequencer
♦ I/O Lines from Host Directly Level Shifted for
Smart Card Communication
♦ Flexible Card Clock Generation, Supporting
External Crystal Frequency Divided by 1, 2, 4, or 8
♦ High-Current/Short-Circuit and High-Temperature
Protection
Pin Configuration
TOP VIEW
CLKDIV1 1
CLKDIV2 2
5V/3V 3
PGND 4
CP2 5
VDDA 6
CP1 7
VUP 8
PRES 9
PRES 10
I/O 11
AUX2 12
AUX1 13
CGND 14
DS8023
SO/TSSOP
28 AUX2IN
27 AUX1IN
26 I/OIN
25 XTAL2
24 XTAL1
23 OFF
22 GND
21 VDD
20 RSTIN
19 CMDVCC
18 1_8V
17 VCC
16 RST
15 CLK
*EMV is a trademark owned by EMVCo LLC. EMV Level 1 library and hardware reference design available. Contact factory for details.
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be
simultaneously available through various sales channels. For information about device errata, go to: www.maxim-ic.com/errata.
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
1 page  
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Smart Card Interface
RECOMMENDED DC OPERATING CONDITIONS (continued)
(VDD = +3.3V, VDDA = +5.0V, TA = +25°C, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
Input Low Current
IIL_IO
VIL = 0V
Input High Current
IIH_IO
VIH = VDD
Input Rise/Fall Time
tIT VIL to VIH
Integrated Pullup Resistor
RPU Pullup to VDD
Current When Pullup Active
IPU CL = 30pF, VOH = 0.9 x VDD
CONTROL PINS (CLKDIV1, CLKDIV2, CMDVCC, RSTIN, 5V/3V)
600 μA
10 μA
1.2 μs
7 11 15 k
-1 mA
Input Low Voltage
VIL
0.3 x
-0.3 VDD V
Input High Voltage
VIH
0.7 x
VDD
VDD +
0.3
V
Input Low Current
Input High Current
INTERRUPT OUTPUT PIN (OFF)
IIL_IO
IIH_IO
0 < VIL < VDD
0 < VIH < VDD
5 μA
5 μA
Output Low Voltage
Output High Voltage
Integrated Pullup Resistor
PRES, PRES PINS
VOL
VOH
RPU
IOL = 2mA
IOH = -15μA
Pullup to VDD
0 0.3 V
0.75 x
VDD
V
15 24 33 k
Input Low Voltage
VIL_PRES
0.3 x
VDD
V
Input High Voltage
Input Low Current
Input High Current
TIMING
VIH_PRES
IIL_PRES
IIH_PRES
VIL_PRES = 0V
VIH_PRES = VDD
0.7 x
VDD
V
5 μA
5 μA
Activation Time
Deactivation Time
CLK to Card Start Window Start
Time
Window End
PRES/PRES Debounce Time
tACT
tDEACT
t3
t5
tDEBOUNCE
160 μs
80 μs
95
μs
160
8 ms
Note 1: Operation guaranteed at TA = -40°C and TA = +85°C, but not tested.
Note 2: IDD_IC measures the amount of current used by the DS8023 to provide the smart card current minus the load.
Note 3: Stop mode is enabled by setting CMDVCC, 5V/3V, and 1_8V to logic-high.
Note 4: Parameters are guaranteed to meet all ISO 7816, GSM11-11, and EMV 2000 requirements. For the 1.8V card, the maximum
rise time and fall time is 10ns.
Note 5: Parameter is guaranteed to meet all ISO 7816, GSM11-11, and EMV 2000 requirements. For the 1.8V card, the minimimum
slew rate is 0.05V/µs and the maximum slew rate is 0.5V/µs.
_______________________________________________________________________________________ 5
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Smart Card Interface
Deactivation Sequence
When the host microcontroller is done communicating
with the smart card, it sets the CMDVCC line high to
execute an automatic deactivation sequence and
returns the card interface to the inactive mode.
The following sequence of events occurs during a
deactivation sequence (Figure 5):
1) RST goes low (t10).
2) CLK is held low (t12 = t10 + 0.5 × T), where T is 64
times the period of the internal oscillator (approxi-
mately 25µs).
3) I/O, AUX1, and AUX2 are pulled low (t13 = t10 + T).
4) VCC starts to fall (t14 = t10 + 1.5 × T).
5) When VCC reaches its inactive state, the deactiva-
tion sequence is complete (at tDE).
6) All card contacts become low impedance to GND;
I/OIN, AUX1IN, and AUX2IN remain at VDD (pulled
up through an internal 11kΩ resistor).
7) The internal oscillator returns to its lower frequency.
VCC Generator
The card voltage (VCC) generator can supply up to
80mA continuously at 5V, 65mA at 3V, or 30mA at 1.8V.
An internal overload detector triggers at approximately
120mA. Current samples to the detector are filtered.
This allows spurious current pulses (with a duration of a
few µs) up to 200mA to be drawn without causing
deactivation. The average current must stay below the
specified maximum current value.
See the Applications Information section for recommen-
dations to help maintain VCC voltage accuracy.
Fault Detection
The DS8023 integrates circuitry to monitor the following
fault conditions:
• Short circuit or high current on VCC
• Card removal while the interface is activated
• VDD dropping below threshold
• Card voltage generator operating out of the speci-
fied values (VDDA too low or current consumption
too high)
• Overheating
There are two different cases for how the DS8023
reacts to fault detection (Figure 6):
• Outside a Card Session (CMDVCC High). Output
OFF is low if a card is not in the card reader and
high if a card is in the reader. The VDD supply is
monitored—a decrease in input voltage generates
an internal power-on reset pulse but does not
affect the OFF signal. Short-circuit and tempera-
ture detection are disabled because the card is
not powered up.
• Within a Card Session (CMDVCC Low). Output
OFF goes low when a fault condition is detected,
and an emergency deactivation is performed auto-
matically (Figure 7). When the system controller
resets CMDVCC to high, it may sense the OFF
level again after completing the deactivation
sequence. This distinguishes between a card
extraction and a hardware problem (OFF goes high
again if a card is present).
Depending on the connector’s card-present switch
(normally closed or normally open) and the mechanical
characteristics of the switch, bouncing can occur on
the PRES signals at card insertion or withdrawal. The
DS8023 has a debounce feature with an 8ms typical
duration (Figure 6). When a card is inserted, output
OFF goes high after the debounce time delay. When
the card is extracted, an automatic deactivation
sequence of the card is performed on the first true/false
transition on PRES and output OFF goes low.
Stop Mode (Low-Power Mode)
A low-power state, stop mode, can be entered by forc-
ing the CMDVCC, 5V/3V, and 1_8V input pins to a
logic-high state. Stop mode can only be entered when
the smart card interface is inactive. In stop mode all
internal analog circuits are disabled. The OFF pin fol-
lows the status of the PRES pin. To exit stop mode,
change the state of one or more of the three control
pins to a logic-low. An internal 220µs (typ) power-up
delay and the 8ms PRES debounce delay are in effect
and OFF is asserted to allow the internal circuitry to sta-
bilize. This prevents smart card access from occurring
after leaving the stop mode. Figure 8 shows the control
sequence for entering and exiting stop mode. Note that
an in-progress deactivation sequence always finishes
before the DS8023 enters low-power stop mode.
______________________________________________________________________________________ 11
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| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet DS8023.PDF ] | |
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