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PDF PSMN7R0-30YL Data sheet ( Hoja de datos )
| Número de pieza | PSMN7R0-30YL | |
| Descripción | N-channel TrenchMOS logic level FET | |
| Fabricantes | NXP Semiconductors | |
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PSMN7R0-30YL
N-channel TrenchMOS logic level FET
Rev. 01 — 15 October 2008
Preliminary data sheet
1. Product profile
1.1 General description
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using TrenchMOS technology. This product is designed and qualified for use in
industrial and communications applications.
1.2 Features and benefits
High efficiency due to low switching
and conduction losses
Suitable for logic level gate drive
sources
1.3 Applications
Class-D amplifiers
DC-to-DC converter
Motor control
Server power supplies
1.4 Quick reference data
Table 1. Quick reference
Symbol Parameter
Conditions
VDS drain-source voltage Tj ≥ 25 °C; Tj ≤ 150 °C
ID drain current
Tmb = 25 °C; VGS = 10 V;
see Figure 1
Ptot total power
dissipation
Tmb = 25 °C; see Figure 2
Dynamic characteristics
QGD
gate-drain charge VGS = 4.5 V; ID = 10 A;
VDS = 12 V; see Figure 14;
see Figure 15
Static characteristics
RDSon
drain-source
on-state resistance
VGS = 10 V; ID = 15 A;
Tj = 25 °C; see Figure 12;
see Figure 13
Min Typ Max Unit
- - 30 V
- - 65 A
- - 51 W
- 2.9 - nC
-
4.7 7
mΩ
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PSMN7R0-30YL
N-channel TrenchMOS logic level FET
6. Characteristics
Table 6. Characteristics
Symbol Parameter
Static characteristics
V(BR)DSS drain-source
breakdown voltage
VGS(th)
gate-source threshold
voltage
IDSS
IGSS
RDSon
drain leakage current
gate leakage current
drain-source on-state
resistance
RG gate resistance
Dynamic characteristics
QG(tot)
total gate charge
QGS
QGS(th)
QGS(th-pl)
QGD
VGS(pl)
Ciss
Coss
Crss
td(on)
tr
td(off)
tf
gate-source charge
pre-threshold
gate-source charge
post-threshold
gate-source charge
gate-drain charge
gate-source plateau
voltage
input capacitance
output capacitance
reverse transfer
capacitance
turn-on delay time
rise time
turn-off delay time
fall time
Conditions
ID = 250 µA; VGS = 0 V; Tj = 25 °C
ID = 250 µA; VGS = 0 V; Tj = -55 °C
ID = 1 mA; VDS = VGS; Tj = 25 °C; see
Figure 10; see Figure 11
ID = 1 mA; VDS = VGS; Tj = 150 °C; see
Figure 10
ID = 1 mA; VDS = VGS; Tj = -55 °C; see
Figure 10
VDS = 30 V; VGS = 0 V; Tj = 25 °C
VDS = 30 V; VGS = 0 V; Tj = 150 °C
VGS = 16 V; VDS = 0 V; Tj = 25 °C
VGS = -16 V; VDS = 0 V; Tj = 25 °C
VGS = 4.5 V; ID = 15 A; Tj = 25 °C; see
Figure 12; see Figure 13
VGS = 10 V; ID = 15 A; Tj = 150 °C; see
Figure 12
VGS = 10 V; ID = 15 A; Tj = 25 °C; see
Figure 12; see Figure 13
f = 1 MHz
ID = 10 A; VDS = 12 V; VGS = 4.5 V; see
Figure 14; see Figure 15
ID = 0 A; VDS = 0 V; VGS = 10 V
ID = 10 A; VDS = 12 V; VGS = 10 V; see
Figure 14; see Figure 15
ID = 10 A; VDS = 12 V; VGS = 4.5 V; see
Figure 14; see Figure 15
VDS = 12 V; see Figure 14; see Figure 15
VDS = 12 V; VGS = 0 V; f = 1 MHz;
Tj = 25 °C; see Figure 16
VDS = 12 V; RL = 0.5 Ω; VGS = 4.5 V;
RG(ext) = 4.7 Ω
PSMN7R0-30YL_1
Preliminary data sheet
Rev. 01 — 15 October 2008
Min Typ Max Unit
30 -
27 -
1.3 1.7
0.65 -
--
--
--
--
--
- 6.7
--
- 4.7
- 0.6
-V
-V
2.15 V
-V
2.45 V
1 µA
100 µA
100 nA
100 nA
11.3 mΩ
12.2 mΩ
7 mΩ
-Ω
- 10 - nC
- 20 - nC
- 22 - nC
- 3.7 - nC
- 2.1 - nC
- 1.6 - nC
- 2.9 - nC
- 2.6 - V
- 1270 - pF
- 255 - pF
- 145 - pF
- 24 - ns
- 39 - ns
- 30 - ns
- 11 - ns
© NXP B.V. 2008. All rights reserved.
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PSMN7R0-30YL
N-channel TrenchMOS logic level FET
8. Revision history
Table 7. Revision history
Document ID
Release date
PSMN7R0-30YL_1
20081015
Data sheet status
Preliminary data sheet
Change notice
-
Supersedes
-
PSMN7R0-30YL_1
Preliminary data sheet
Rev. 01 — 15 October 2008
© NXP B.V. 2008. All rights reserved.
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