|
|
PDF CY8C22213 Data sheet ( Hoja de datos )
| Número de pieza | CY8C22213 | |
| Descripción | (CY8C22113 / CY8C22213) PSoC Mixed Signal Array | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de CY8C22213 (archivo pdf) en la parte inferior de esta página. Total 70 Páginas | ||
|
No Preview Available !
www.DataSheet4U.com
CY8C22113, CY8C22213
PSoC™ Mixed Signal Array
Preliminary Data Sheet
For Silicon Revision A
December 22, 2003
Cypress MicroSystems
2700 162nd Street SW
Building D
Lynnwood, WA 98037
Phone: 800.669.0557
FAX: 425.787.4641
http://www.cypress.com
Document No. 38-12009 Rev. *D
1 page  
CY8C22xxx Preliminary Data Sheet
Contents
www.DataSheet4U.com
9. Internal Low Speed Oscillator (ILO) ........................................................................65
9.1 Architectural Description ......................................................................................................65
9.2 Register Definitions ..............................................................................................................65
9.2.1 ILO_TR Register ............................................................................................65
10. 32 kHz Crystal Oscillator (ECO) ..............................................................................67
10.1 Architectural Description ......................................................................................................67
10.1.1 ECO External Components............................................................................68
10.2 Register Definitions ..............................................................................................................68
10.2.1 OSC_CR0 Register........................................................................................68
10.2.2 ECO_TR Register ..........................................................................................69
10.2.3 CPU_SCR1 Register......................................................................................69
11. Phase Locked Loop (PLL) .......................................................................................71
11.1 Architectural Description ......................................................................................................71
11.2 Register Definitions ..............................................................................................................71
11.2.1 OSC_CR0 Register........................................................................................71
11.2.2 OSC_CR2 Register........................................................................................72
12. Sleep and Watchdog ..............................................................................................73
12.1
12.2
12.3
12.4
12.5
Architectural Description ......................................................................................................73
12.1.1 32 kHz Clock Selection ..................................................................................73
12.1.2 Sleep Timer ....................................................................................................74
12.1.3 Sleep Bit.........................................................................................................74
Application Description.........................................................................................................74
Register Definitions ..............................................................................................................75
12.3.1 INT_MSK0 Register .......................................................................................75
12.3.2 RES_WDT Register .......................................................................................75
12.3.3 OSC_CR0 Register........................................................................................75
12.3.4 CPU_SCR1 Register......................................................................................76
12.3.5 ILO_TR Register ............................................................................................76
12.3.6 ECO_TR Register ..........................................................................................76
12.3.7 CPU_SCR0 Register......................................................................................76
Timing Diagrams ..................................................................................................................77
12.4.1 Sleep Sequence.............................................................................................77
12.4.2 Wake Up Sequence .......................................................................................78
12.4.3 Bandgap Refresh ...........................................................................................79
12.4.4 Watchdog Timer (WDT) .................................................................................79
Power Consumption.............................................................................................................80
SECTION C REGISTER REFERENCE
81
Register Conventions .......................................................................................................................81
Register Mapping Tables .................................................................................................................81
Register Map 0 Table: User Space ..............................................................................82
Register Map 1 Table: Configuration Space ................................................................83
13. Register Details ......................................................................................................85
13.1 Bank 0 Registers..................................................................................................................86
13.1.1 PRTxDR ........................................................................................................86
13.1.2 PRTxIE ..........................................................................................................87
13.1.3 PRTxGS ........................................................................................................88
December 22, 2003
Document No. 38-12009 Rev. *D
5
5 Page 
CY8C22xxx Preliminary Data Sheet
Contents
www.DataSheet4U.com
29. System Resets ..................................................................................................... 281
29.1
29.2
29.3
Register Definitions ............................................................................................................281
29.1.1 CPU_SCR0 Register....................................................................................281
29.1.2 CPU_SCR1 Register....................................................................................282
Timing Diagrams ................................................................................................................282
29.2.1 Power On Reset (POR)................................................................................282
29.2.2 External Reset (XRES) ................................................................................282
29.2.3 Watchdog Timer Reset (WDR).....................................................................282
29.2.4 Reset Details ................................................................................................284
Power Consumption...........................................................................................................285
SECTION G ELECTRICAL SPECIFICATIONS
287
Absolute Maximum Ratings .........................................................................................................288
Operating Temperature ................................................................................................................288
DC Electrical Characteristics ..........................................................................................................289
DC Chip-Level Specifications ............................................................................................289
DC General Purpose IO (GPIO) Specifications ................................................................289
DC Operational Amplifier Specifications ...........................................................................290
DC Analog Output Buffer Specifications ...........................................................................292
DC Analog Reference Specifications ................................................................................293
DC Analog PSoC Block Specifications .............................................................................293
DC POR and LVD Specifications ......................................................................................294
DC Programming Specifications .......................................................................................295
AC Electrical Characteristics ..........................................................................................................296
AC Chip-Level Specifications ............................................................................................296
AC General Purpose IO (GPIO) Specifications .................................................................296
AC Operational Amplifier Specifications ...........................................................................297
AC Digital Block Specifications .........................................................................................299
AC Analog Output Buffer Specifications ...........................................................................300
AC External Clock Specifications ......................................................................................301
AC Programming Specifications .......................................................................................301
AC I2C Specifications .......................................................................................................302
SECTION H REVISION HISTORY
303
December 22, 2003
Document No. 38-12009 Rev. *D
11
11 Page | ||
| Páginas | Total 70 Páginas | |
| PDF Descargar | [ Datasheet CY8C22213.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| CY8C22213 | (CY8C22113 / CY8C22213) PSoC Mixed Signal Array | Cypress Semiconductor |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |