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PDF CY8C20140 Data sheet ( Hoja de datos )
| Número de pieza | CY8C20140 | |
| Descripción | Configurable IOs | |
| Fabricantes | Cypress Semiconductor | |
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CY8C20140
CapSense Express™ - 4 Configurable IOs
Features
■ 4 configurable IOs supporting
❐ CapSense buttons
❐ LED drive
❐ Interrupt outputs
❐ WAKE on interrupt input
❐ User defined Input or output
■ 2.4V to 5.25V operating voltage
■ Industrial temperature range: –40°C to +85°C
■ I2C slave interface for configuration
■ Reduce BOM cost
❐ Internal oscillator - no external oscillators or crystal
❐ Free development tool - no external tuning components
■ Low Operating Current
❐ Active current: continuous sensor scan:1.5 mA
❐ Sleep current: no scan, continuous sleep:2.6 uA
■ Available in 16-pin COL and 16-pin SOIC packages
Overview
The CapSense ExpressTM controller allows the control of 4 IOs
configurable as capacitive sensing buttons or as GPIOs for
driving LEDs or interrupt signals based on various button
conditions. The GPIOs are also configurable for waking up the
device from sleep based on an interrupt input.
The user has the ability to configure buttons, outputs, and
parameters, through specific commands sent to the I2C port. The
IOs have the flexibility in mapping to capacitive buttons and as
standard GPIO functions such as interrupt output or input, LED
drive and digital mapping of input to output using simple logical
operations. This enables easy PCB trace routing and reduces
the PCB size and stack up. CapSense Express products are
designed for easy integration into complex products.
Architecture
The logic block diagram shows the internal architecture of
CY8C20140.
The user can configure registers with parameters needed to
adjust the operation and sensitivity of the CapSense system.
CY8C20140 supports a standard I2C serial communication
interface that allows the host to configure the device and to read
sensor information in real time through easy register access.
The CapSense Express Core
The CapSense Express Core has a powerful configuration and
control block. It encompasses SRAM for data storage, an
interrupt controller, sleep, and watchdog timers. System
resources provide additional capability, such as a configurable
I2C slave communication interface and various system resets.
The Analog System is composed of the CapSense PSoC block
which supports capacitive sensing of up to 4 inputs.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-17348 Rev. *C
• San Jose, CA 95134-1709 • 408-943-2600
Revised March 11, 2008
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CY8C20140
The CapSense Analog System
The CapSense analog system contains the capacitive sensing
hardware which supports CapSense Successive Approximation
(CSA) algorithm. This hardware performs capacitive sensing and
scanning without external components. Capacitive sensing is
configurable on each pin.
Additional System Resources
System resources provide additional capability useful to
complete systems. Additional resources are low voltage
detection and power on reset.
■ The I2C slave provides 50, 100, or 400 kHz communication
over two wires.
■ Low Voltage Detection (LVD) interrupts can signal the appli-
cation of falling voltage levels and the advanced POR (Power
On Reset) circuit eliminates the need for a system supervisor.
An internal 1.8V reference provides an absolute reference for
capacitive sensing. By this we are telling we have a stable internal
reference, so that minor VDD changes does not alter the function-
ality of CapSense.
Electrical Specifications
I2C Interface
The two modes of operation for the I2C interface are:
■ Device register configuration and status read or write for
controller
■ Command execution
The I2C address is programmable during configuration. It can be
locked to prevent accidental change by setting a flag in a config-
uration register.
CapSense Express Software Tool
An easy to use software tool integrated with PSoC Express is
available for configuring and tuning CapSense Express devices.
Refer to the Application Note AN42137 for details of the software
tool.
CapSense Express Register Map
CapSense Express supports user configurable registers through
which the device functionality and parameters are configured.
For details, refer to CY8C201xx Register Reference document.
Absolute Maximum Ratings
Parameter
Description
Min Typ Max Unit
Notes
TSTG
Storage temperature
–55 25 +100 °C Higher storage temperatures reduce
data retention time. Recommended
storage temperature is +25°C ± 25°C
(0°C to 50°C). Extended duration
storage temperatures above 65°C
degrade reliability.
TA
Ambient temperature with power
–40 – +85 °C
applied
VDD
VIO
VIOZ
IMIO
ESD
Supply voltage on VDD relative to VSS –0.5
–
+6.0
V
DC input voltage
VSS – 0.5 – VDD + 0.5 V
DC voltage applied to tri-state
VSS – 0.5 – VDD + 0.5 V
Maximum current into any GPIO pin –25 – +50 mA
Electro static discharge voltage
2000 –
–
V Human body model ESD
LU Latch up current
– – 200 mA
Operating Temperature
Parameter
Description
TA Ambient temperature
TJ Junction temperature
Min Typ Max Unit
–40 – +85 °C
–40 – +100 °C
Notes
Document Number: 001-17348 Rev. *C
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CY8C20140
Ordering Information
Ordering Code
CY8C20140-LDX2I
CY8C20140-SX2I
Package Diagram
001-09116
51-85068
Package Type
16 COL[3]
16 SOIC
Operating
Temperature
Industrial
Industrial
Thermal Impedances by Package
Package
16 COL[3]
16 SOIC
Solder Reflow Peak Temperature
Package
16 COL[3]
16 SOIC
Minimum Peak Temperature[2]
240 °C
240 °C
Typical θJA[1]
46 °C
79.96 °C
Maximum Peak Temperature
260 °C
260 °C
Notes
1. TJ = TA + Power x θJA.
2. Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220 ± 5°C with Sn-Pb or 245 ± 5°C with Sn-Ag-Cu paste.
Refer to the solder manufacturer specifications.
3. Earlier termed as QFN package.
Document Number: 001-17348 Rev. *C
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