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PDF VSP5000 Data sheet ( Hoja de datos )
| Número de pieza | VSP5000 | |
| Descripción | 12-BIT 30 MSPS DUAL CHANNEL CCD SIGNAL FRONT END | |
| Fabricantes | Burr-Brown Corporation | |
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VSP5000
SLES057 – DECEMBER 2002
12-BIT 30 MSPS DUAL CHANNEL
CCD SIGNAL FRONT END FOR DIGITAL COPIER
FEATURES
D Dual Channel CCD Signal Processing:
– Correlated Double Sampler (CDS)
– Sample Hold Mode
– Digital Programmable Amplifier
– CCD Offset Correction (OB loop)
D High Performance A/D:
– 12-Bit Resolution
– INL: ±2 LSB
– DNL: ±0.5 LSB
– No Missing Codes
D High-Speed Operation
– Sample Rate: 30 MHz (Minimum)
D 78-dB Signal-To-Noise Ratio (at 0-dB Gain)
D Low Power Consumption:
– Low Voltage: 3 V to 3.6 V
– Low Power: 290 mW (Typ) at 3.3 V
– Standby Mode: 20 mW (Typ)
APPLICATIONS
D Copiers
D Scanners
D Facsimiles
DESCRIPTION
The VSP5000 device is a complete application specific
standard product (ASSP) for charge-coupled device
(CCD) line sensor applications such as copiers, scanners,
and facsimiles. The VSP5000 device provides two
independent channels of processing lines and performs
analog front-end processing and analog-to-digital (A/D)
conversion. Each channel has a correlated double
sampler (CDS)/sample hold (SH) circuit, a 14-bit
analog-to-digital converter (ADC), a digital programmable
gain amplifier (DPGA), and an optical black (OB)
correction loop. Data output is 12 bits in length and the
2-channel A/D data is multiplexed and output.
The VSP5000 is available in a 64-lead LQFP package and
operates from a single 3.3-V supply.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products
conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters.
Copyright 2002, Texas Instruments Incorporated
1 page  
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FUNCTIONAL BLOCK DIAGRAM
VSP5000
SLES057 – DECEMBER 2002
SCLK SDI RDO WRT
BYPP_EV COB_EV BYPM_EV BYP_EV REFP_EV CM_EV
REFN_EV
CA0
CA1
RESET
Serial
Interface
CCD
Out Signal
Clamp
CCDIN_EV
CDS/SH SEL
CLPOB
INPUTCLP
SHP
SHD
SYSCLK
CCDIN_OD
CCD
Out Signal
Clamp
Even Channel
Internal Reference
Current
Buf
D-to-A
Decoder
Converter
CDS/SH
14-Bit
A-to-D
Converter
Timing / Control
CDS/SH
14-Bit
A-to-D
Converter
Digital
PGA
Digital
PGA
Output
Register
OUTENB
Output
Control
Output
Register
12-Bit
Digital
Output
Current
Buf
D-to-A
Decoder
Converter
Odd Channel
Internal Reference
BYPP_OD COB_OD BYPM_OD BYP_OD REFP_OD CM_OD
REFN_OD
5
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VSP5000 Serial Interface Timing Specification 2 (Read)
tsu(X)
WRT
tsu(XW)
tw(CKH)
tw(CKL)
tw(WR)
th(X)
SCLK
SD
1
MSB
(CA1)
2
tsu(D)
t(CKP)
2 Bytes
15 16
th(D)
LSB
(D0)
tsu(R)
RD
tsu(X)
VSP5000
SLES057 – DECEMBER 2002
tw(CKH)
12
9
tw(CKH)
10
t(CKP)
MSB
(D9)
10 Bits
LSB
(D0)
SYMBOL
t(CKP)
tw(CKH)
tw(CKL)
tsu(D)
th(D)
tsu(X)
th(X)
tsu(XW)
tw(WR)
tsu(R)
Clock period
Clock high pulse width
Clock low pulse width
Data setup time (write)
Data hold time (write)
WRT to SCLK setup time
SCLK to WRT hold time
WRT setup time
Minimum WRT width
Data setup time (read)
PARAMETER
MIN TYP MAX UNIT
100 ns
40 ns
40 ns
30 ns
30 ns
15 ns
15 ns
15 ns
10 ns
30 ns
11
11 Page | ||
| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet VSP5000.PDF ] | |
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