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PDF ADAU1401 Data sheet ( Hoja de datos )
| Número de pieza | ADAU1401 | |
| Descripción | SigmaDSP 28-/56-Bit Audio Processor | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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SigmaDSP 28-/56-Bit Audio Processor
with Two ADCs and Four DACs
ADAU1401
FEATURES
GENERAL DESCRIPTION
28-/56-bit, 50 MIPS digital audio processor
2 ADCs: SNR of 100 dB, THD + N of −83 dB
4 DACs: SNR of 104 dB, THD + N of −90 dB
Complete standalone operation
Self-boot from serial EEPROM
Auxiliary ADC with 4-input mux for analog control
The ADAU1401 is a complete single-chip audio system with a
28-/56-bit audio DSP, ADCs, DACs, and microcontroller-like
control interfaces. Signal processing includes equalization, cross-
over, bass enhancement, multiband dynamics processing, delay
compensation, speaker compensation, and stereo image widening.
GPIOs for digital controls and outputs
This processing can be used to compensate for real-world
Fully programmable with SigmaStudio graphical tool
28-bit × 28-bit multiplier with 56-bit accumulator for full
double-precision processing
Clock oscillator for generating master clock from crystal
limitations of speakers, amplifiers, and listening environments,
providing dramatic improvements in perceived audio quality.
Its signal processing is comparable to that found in high
PLL for generating master clock from 64 × fS, 256 × fS,
384 × fS, or 512 × fS clocks
Flexible serial data input/output ports with I2S-compatible,
left-justified, right-justified, and TDM modes
Sampling rates of up to 192 kHz supported
On-chip voltage regulator for compatibility with 3.3 V systems
end studio equipment. Most processing is done in full 56-bit,
double-precision mode, resulting in very good low level signal
performance. The ADAU1401 is a fully programmable DSP. The
easy to use SigmaStudio™ software allows the user to graphically
configure a custom signal processing flow using blocks such as
48-lead, plastic LQFP
biquad filters, dynamics processors, level controls, and GPIO
APPLICATIONS
interface controls.
Multimedia speaker systems
MP3 player speaker docks
ADAU1401 programs can be loaded on power-up either from a
serial EEPROM through its own self-boot mechanism or from
Automotive head units
an external microcontroller. On power-down, the current state
Minicomponent stereos
Digital televisions
Studio monitors
Speaker crossovers
of the parameters can be written back to the EEPROM from the
ADAU1401 to be recalled the next time the program is run.
Two Σ-Δ ADCs and four Σ-Δ DACs provide a 98.5 dB analog
Musical instrument effects processors
In-seat sound systems (aircraft/motor coaches)
input to analog output dynamic. Each ADC has a THD + N of
−83 dB, and each DAC has a THD + N of −90 dB. Digital input
and output ports allow a glueless connection to additional
ADCs and DACs. The ADAU1401 communicates through an
I2C® bus or a 4-wire SPI port.
FUNCTIONAL BLOCK DIAGRAM
PLL
DIGITAL DIGITALANALOG ANALOG PLL LOOP
3.3V VDD GROUND VDD GROUND MODE FILTER
3
33
33
CRYSTAL
2
1.8V
REGULATOR
2-CHANNEL
ANALOG
INPUT
FILTA/
ADC_RES 2
STEREO
ADC
ADAU1401
PLL
28-/56-BIT, 50MIPS
AUDIO PROCESSOR CORE
40ms DELAY MEMORY
CLOCK
OSCILLATOR
DAC
DAC
2 FILTD/CM
4-CHANNEL
ANALOG
OUTPUT
RESET/
MODE
SELECT
CONTROL
INTERFACE
AND
SELFBOOT
8-CH
DIGITAL
INPUT
8-BIT
AUX
ADC
GPIO
8-CH
DIGITAL
OUTPUT
INPUT/OUTPUT MATRIX
5
RESET SELF
I2C/SPI
BOOT
AND
WRITEBACK
444
DIGITAL IN AUX ADC DIGITAL OUT
OR OR OR
GPIO
GPIO
GPIO
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2007 Analog Devices, Inc. All rights reserved.
1 page  
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ADAU1401
POWER
Table 4.
Parameter
SUPPLY VOLTAGE
Analog Voltage
Digital Voltage
PLL Voltage
IOVDD Voltage
SUPPLY CURRENT
Analog Current (AVDD and PVDD)
Digital Current (DVDD)
Analog Current, Reset
Digital Current, Reset
DISSIPATION
Operation (AVDD, DVDD, PVDD)2
Reset, All Supplies
POWER SUPPLY REJECTION RATIO (PSRR)
1 kHz, 200 mV p-p Signal at AVDD
Min Typ
3.3
1.8
3.3
3.3
50
40
35
1.5
286.5
118
50
Max1
85
60
55
4.5
Unit
V
V
V
V
mA
mA
mA
mA
mW
mW
dB
1 Maximum specifications are measured across a temperature range of −40°C to +130°C (case), a DVDD range of 1.62 V to 1.98 V, and an AVDD range of 2.97 V to 3.63 V.
2 Power dissipation does not include IOVDD power because the current drawn from this supply is dependent on the loads at the digital output pins.
TEMPERATURE RANGE
Table 5.
Parameter
Functionality Guaranteed
Min Typ Max Unit
−40 105 °C ambient
PLL AND OSCILLATOR
Table 6. PLL and Oscillator1
Parameter
PLL Operating Range
PLL Lock Time
Crystal Oscillator Transconductance (gm)
Min Typ
MCLK_Nom − 20%
78
Max
MCLK_Nom + 20%
20
Unit
MHz
ms
mmho
1 Maximum specifications are measured across a temperature range of −40°C to +130°C (case), a DVDD range of 1.62 V to 1.98 V, and an AVDD range of 2.97 V to 3.63 V.
REGULATOR
Table 7. Regulator1
Parameter
DVDD Voltage
Min Typ
1.7 1.8
1 Regulator specifications are calculated using a Zetex Semiconductors FZT953 transistor in the circuit.
Max
1.84
Unit
V
Rev. 0 | Page 5 of 52
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ADAU1401
Pin No.
14
15
16
17
18
19
20
21
22
23
26
27
28
29
30
31
32
33
34
35
36, 48
Mnemonic
MP7
MP6
MP10
VDRIVE
IOVDD
MP11
ADDR1/CDATA/WB
CLATCH/WP
SDA/COUT
SCL/CCLK
MP9
MP8
MP3
MP2
RSVD
OSCO
MCLKI
PGND
PVDD
PLL_LF
AVDD
Type 1
D_IO
D_IO
D_IO
A_OUT
PWR
D_IO
D_IN
D_IO
D_IO
D_IO
D_IO/A_IO
D_IO/A_IO
D_IO/A_IO
D_IO/A_IO
X
D_OUT
D_IN
PWR
PWR
A_OUT
PWR
Page No.
44
44
44
18
44
22, 25, 26
24, 26
22, 25
22, 25
44
44
44
44
17
17
17
Description
Multipurpose GPIO or Serial Output Port Data 1 (SDATA_OUT1).
Multipurpose GPIO, Serial Output Port Data 0, or TDM Data Output
(SDATA_OUT0).
Multipurpose GPIO or Serial Output Port LRCLK (OUTPUT_LRCLK).
Drive for 1.8 V Regulator. The base of the voltage regulator external PNP
transistor is driven from VDRIVE.
Supply for Input and Output Pins. The voltage on this pin sets the highest
input voltage that should be seen on the digital input pins. This pin is also
the supply for the digital output signals on the control port and MP pins.
IOVDD should always be set to 3.3 V. The current draw of this pin is variable
because it is dependent on the loads of the digital outputs.
Multipurpose GPIO or Serial Output Port BCLK (OUTPUT_BCLK).
ADDR1: I2C Address 1. In combination with ADDR0, this sets the I2C address
of the IC so that four ADAU1401s can be used on the same I2C bus.
CDATA: SPI Data Input.
WB: EEPROM Writeback Trigger. A rising (default) or falling (if set in the
EEPROM messages) edge on this pin triggers a writeback of the interface
registers to the external EEPROM. This function can be used to save
parameter data on power-down.
CLATCH: SPI Latch Signal. Must go low at the beginning of an SPI transaction
and high at the end of a transaction. Each SPI transaction can take a different
number of CCLKs to complete, depending on the address and read/write bit
that are sent at the beginning of the SPI transaction.
WP: Self-Boot EEPROM Write Protect. This pin is an open-collector output
when in self-boot mode. The ADAU1401 pulls this low to prohibit writes to
an external EEPROM. This pin should be pulled high to 3.3 V.
SDA: I2C Data. This pin is a bidirectional open-collector. The line connected
to this pin should have a 2.2 kΩ pull-up resistor.
COUT: This SPI data output is used for reading back registers and memory
locations. It is three-stated when an SPI read is not active.
SCL: I2C Clock. This pin is always an open-collector input when in I2C control
mode. In self-boot mode, this pin is an open-collector output (I2C master).
The line connected to this pin should have a 2.2 kΩ pull-up resistor.
CCLK: SPI Clock. This pin can either run continuously or be gated off
between SPI transactions.
Multipurpose GPIO, Serial Output Port Data 3 (SDATA_OUT3), or Auxiliary
ADC Input 0.
Multipurpose GPIO, Serial Output Port Data 2 (SDATA_OUT2), or Auxiliary
ADC Input 3.
Multipurpose GPIO, Serial Input Port Data 3 (SDATA_IN3), or Auxiliary
ADC Input 2.
Multipurpose GPIO, Serial Input Port Data 2 (SDATA_IN2), or Auxiliary
ADC Input 1.
Reserved. Tie to ground, either directly or through a pull-down resistor.
Crystal Oscillator Circuit Output. A 100 Ω damping resistor should be
connected between this pin and the crystal. This output should not be used
to directly drive a clock to another IC. If the crystal oscillator is not used, this
pin can be left disconnected.
Master Clock Input. MCLKI can either be connected to a 3.3 V clock signal or
be the input from the crystal oscillator circuit.
PLL Ground Pin. The AGND, DGND, and PGND pins can be tied directly
together in a common ground plane. PGND should be decoupled to PVDD
with a 100 nF capacitor.
3.3 V Power Supply for the PLL and the Auxiliary ADC Analog Section. This
should be decoupled to PGND with a 100 nF capacitor.
PLL Loop Filter Connection. Two capacitors and a resistor need to be connected
to this pin, as shown in Figure 15.
3.3 V Analog Supply. This should be decoupled to AGND with a 100 nF capacitor.
Rev. 0 | Page 11 of 52
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| PDF Descargar | [ Datasheet ADAU1401.PDF ] | |
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