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PDF CY8CNP102B Data sheet ( Hoja de datos )
| Número de pieza | CY8CNP102B | |
| Descripción | Nonvolatile Programmable System-on-Chip | |
| Fabricantes | Cypress Semiconductor | |
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PRELIMINARY
CY8CNP102B, CY8CNP102E
Nonvolatile Programmable System-on-Chip
(PSoC® NV)
Overview
The Cypress nonvolatile Programmable System-on-Chip
(PSoC® NV) processor combines a versatile Programmable
System-on-Chip™ (PSoC) core with an infinite endurance
nvSRAM in a single package. The PSoC NV combines an 8-bit
MCU core (M8C), configurable analog and digital functions, a
uniquely flexible IO interface, and a high density nvSRAM. This
creates versatile data logging solutions that provide value
through component integration and programmability. The flexible
core and a powerful development environment work to reduce
design complexity, component count, and development time.
Features
■ Powerful Harvard Architecture Processor
❐ M8C processor speeds
• Up to 12 MHz for 3.3V operation
• Up to 24 MHz for 5V operation
❐ Two 8x8 multiply, 32 bit accumulate
❐ Low power at high speed
■ Operating Voltage
❐ 3.3V (CY8CNP102B)
❐ 5V (CY8CNP102E)
■ Advanced Peripherals
❐ 12 Rail-to-Rail Analog PSoC blocks provide:
• Up to 14 bit ADCs
• Up to 9 bit DACs
• Programmable Gain Amplifiers
• Programmable Filters and Comparators
• 8 Analog channels for simultaneous sampling
• Up to 820 SPS for each channel with 8 channel sampling
and logging
❐ 16 Digital PSoC Blocks provide:
• 8 to 32 bit timers, counters, and PWMs
• CRC and PRS Modules
• Up to 4 Full Duplex UARTs
• Multiple SPI™ Masters and Slaves
❐ Complex Peripherals by Combining Blocks
■ Precision, Programmable Clocking
❐ Internal ±2.5% 24 and 48 MHz Oscillator
❐ 24 and 48 MHz with optional 32.768 kHz Crystal
❐ Optional External Oscillator, up to 24 MHz
❐ Internal Oscillator for Watchdog and Sleep
■ Flexible On-Chip Memory
❐ 32K Bytes Flash Program Storage
❐ 2K Bytes SRAM Data Storage
❐ 256K Bytes secure store nvSRAM with data throughput be-
tween 100 KBPS and 1 MBPS
❐ In-System Serial Programming (ISSP)
❐ Partial Flash Updates
❐ Flexible Protection Modes
❐ EEPROM Emulation in Flash
■ Programmable Pin Configurations
❐ 33 GPIOs
❐ 25 mA Sink on all GPIO
❐ Pull up, Pull down, High Z, Strong, or Open Drain Drive
Modes on all GPIO
❐ Up to 12 Analog Inputs on GPIOs
❐ Analog Outputs with 40 mA on 4 GPIOs
❐ Configurable Interrupt on all GPIOs
■ Additional System Resources
❐ I2C Slave, Master, and MultiMaster to 100 Kbps
and 400 Kbps
❐ Watchdog and Sleep Timers
❐ Integrated Supervisory Circuit
❐ On-Chip Precision Voltage Reference
■ Complete Development Tools
❐ Free Development Software (PSoC Designer™)
❐ Full Featured, In Circuit Emulator and Programmer
❐ Full Speed Emulation
❐ C Compilers, Assembler, and Linker
■ Temperature and Packaging
❐ Industrial Temperature Range: -40°C to +85°C
❐ Packaging: 100-pin TQFP
Cypress Semiconductor Corporation • 198 Champion Court
Document #: 001-43991 Rev. *D
• San Jose, CA 95134-1709 • 408-943-2600
Revised October 20, 2008
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PRELIMINARY CY8CNP102B, CY8CNP102E
Table 1. Pin Definitions - 100-Pin TQFP (continued)
Pin Number Pin Name
79
80
81 - 85
86 - 90
91 - 98
99
100
HSB#
Vcc
NC
Vss
NC
NV_C
P0_7
Type
Digital
Analog
Power
Power
IO I
Pin Definition
Weak Pull up. Connect 10kΩ to Vcc.
Supply Voltage
Not connected on the die
Ground
Not connected on the die
Connect to Pin 61 (NV_C to EN_C).Weak Pull up. Connect 10kΩ to Vcc.
Analog Column Mux Input, GPIO
PSoC NV Functional Overview
The PSoC NV provides a versatile microcontroller core (M8C),
Flash program memory, nvSRAM data memory, and
configurable analog and digital peripheral blocks in a single
package. The flexible digital and analog IOs and routing matrix
create a powerful embedded and flexible mixed signal
System-on-Chip (SoC).
The device incorporates configurable analog and digital blocks,
interconnect circuitry around an MCU subsystem, and an infinite
endurance nvSRAM. This enables high level integration in
consumer, industrial, and automotive applications, where
preventing data loss under all conditions is vital.
PSoC NV Core
The PSoC NV core is a powerful PSoC engine that supports a
rich feature set. The core includes a M8C CPU, memory, clocks,
and configurable GPIO (General Purpose IO). The M8C CPU
core is a powerful processor with speeds up to 24 MHz, providing
a four MIPS 8-bit Harvard architecture microprocessor. The CPU
uses an interrupt controller with 25 vectors, to simplify
programming of real time embedded events. Program execution
is timed and protected using the included Sleep and Watch Dog
Timers (WDT).
On-chip memory encompasses 32 KB Flash for program
storage, 2 KB SRAM for data storage, 256 KB nvSRAM for data
logging, and up to 2 KB EEPROM emulated using Flash.
Program Flash uses four protection levels on blocks of 64 bytes,
allowing customized software IP protection. The nvSRAM
combines a static RAM cell and a SONOS cell to provide an
infinite endurance nonvolatile memory block. The memory is
random access and is accessed using a user module provided
with the device.
The device incorporates flexible internal clock generators,
including a 24 MHz Internal Main Oscillator (IMO) accurate to 2.5
percent over temperature and voltage. The 24 MHz IMO can also
be doubled to 48 MHz for use by the digital system. A low power
32 kHz Internal Low speed Oscillator (ILO) is provided for the
Sleep timer and WDT. The clocks, together with programmable
clock dividers (as a System Resource), provide the flexibility to
integrate almost any timing requirement into the PSoC NV
device.
GPIOs provide connection to the CPU, and digital and analog
resources of the device. Each pin’s drive mode may be selected
from eight options, allowing great flexibility in external
interfacing. Every pin also has the capability to generate a
system interrupt on high level, low level, and change from last
read.
nvSRAM Data Memory
The nvSRAM memory block is byte addressable fast static RAM
with a nonvolatile element in each memory cell. The embedded
nonvolatile elements incorporate QuantumTrap® technology
producing the world’s most reliable nonvolatile memory. The
SRAM provides infinite read and write cycles, when independent
nonvolatile data resides in the highly reliable QuantumTrap cell.
Data transfers from the SRAM to the nonvolatile elements (the
STORE operation) takes place automatically at power down, and
data is restored to the SRAM (the RECALL operation) from the
nonvolatile memory on power up. All cells store and recall data
in parallel.
Both the STORE and RECALL operations may be initiated under
software control. The PSoC NV user module embedded in the
PSoC Designer Tool provides all necessary APIs to initiate
software STORE and RECALL function from the user program.
nvSRAM Operation
The nvSRAM is made up of an SRAM memory cell, and a
nonvolatile QuantumTrap cell paired in the same physical cell.
The SRAM memory cell operates as a standard fast static, and
all READ and WRITE takes place from the SRAM during normal
operation.
During the STORE and RECALL operations, SRAM READ and
WRITE operations are inhibited, and internal operations transfer
data between the SRAM and nonvolatile cells. The nvSRAM
provides infinite RECALL operations from the nonvolatile cells
and up to 200,000 STORE operations.
To reduce unnecessary nonvolatile stores, AutoStore® is ignored
unless at least one WRITE operation is complete after the most
recent STORE or RECALL cycle. Software initiated STORE
cycles are performed regardless of whether a WRITE operation
has taken place. Embedded APIs provide a seamless interface
to the nvSRAM.
During normal operation, the embedded nvSRAM draws current
from Vcc to charge a capacitor connected to the VCAP pin. This
stored charge is used by the chip to perform a STORE operation.
If the voltage on the Vcc pin drops below VSWITCH, the part
automatically disconnects the VCAP pin from Vcc and STORE
operation is initiated.
Document #: 001-43991 Rev. *D
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PRELIMINARY CY8CNP102B, CY8CNP102E
DC Electrical Characteristics
The following DC electrical specifications list the guaranteed maximum and minimum specifications for the voltage and temperature
range: 3.0V to 3.6V over the Temperature range of -40°C ≤ TA ≤ 85°C. Typical parameters apply to 3.3V at 25°C and are for design
guidance only.
DC Chip Level Specifications
Table 5. 3.3V DC Chip Level Specifications (CY8CNP102B)
Symbol
Vcc
IDD
Description
Supply Voltage
Supply Current
Min
3.00
–
IDDP
Supply current when IMO = 6 MHz
using SLIMO mode.
–
ISB
VREF
Vcap
Sleep (Mode) Current with POR, LVD,
Sleep Timer, WDT, and internal slow
oscillator active.
Reference Voltage (Bandgap)
Storage Capacitor between Vcap and
Vss
–
1.28
61
Typ Max Units
Notes
– 3.6 V
36 40 mA TA = 25 oC, CPU = 3 MHz,
SYSCLK doubler disabled,
VC1 = 1.5 MHz, VC2 = 93.75 kHz,
VC3 = 0.366 kHz, continuous
nvSRAM access
27 28 mA TA = 25 oC, CPU = 0.75 MHz,
SYSCLK doubler disabled,
VC1=0.375 MHz, VC2=23.44 kHz,
VC3 = 0.09 kHz, continuous
nvSRAM access
– 5 mA nvSRAM in standby.
1.3 1.32
68 82
V Trimmed for appropriate Vcc.
uF 5V rated (minimum)
DC General Purpose IO Specifications
Table 6. 3.3V DC GPIO Specifications (CY8CNP102B)
Symbol
RPU
RPD
VOH
Description
Pull up Resistor
Pull down Resistor
High Output Level
VOL Low Output Level
VIL
VIH
VH
IIL
CIN
COUT
Input Low Level
Input High Level
Input Hysterisis
Input Leakage (Absolute Value)
Capacitive Load on Pins as Input
Capacitive Load on Pins as Output
Min Typ Max Units
Notes
4 5.6 8 KΩ
4 5.6 8 KΩ
Vcc - 1.0
–
–
V IOH = 10 mA, Vcc = 3.0 to 3.6V. 8
total loads, 4 on even port pins (for
example, P0[2], P1[4]), 4 on odd
port pins (for example, P0[3],
P1[5]). 80 mA maximum combined
IOH budget.
–
– 0.75
V IOL = 25 mA, Vcc = 3.0 to 3.6V
8 total loads, 4 on even port pins
(for example, P0[2], P1[4]), 4 on
odd port pins (for example, P0[3],
P1[5]). 150 mA maximum
combined IOL budget.
– – 0.8 V Vcc = 3.0 to 3.6
1.6 –
V Vcc = 3.0 to 3.6
– 60 – mV
– 1 – nA Gross tested to 1 μA.
–
3.5 10
pF Pin dependent.
Temp = 25oC.
–
3.5 10
pF Pin dependent.
Temp = 25oC.
Document #: 001-43991 Rev. *D
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| PDF Descargar | [ Datasheet CY8CNP102B.PDF ] | |
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