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PDF CYRF69103 Data sheet ( Hoja de datos )
| Número de pieza | CYRF69103 | |
| Descripción | Programmable Radio on Chip Low Power | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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PRoC™ LP Features
• Single Device, Two Functions
— 8-bit, Flash based MCU function and 2.4 GHz radio
transceiver function in a single device.
• Flash-Based Microcontroller Function
— M8C based 8-bit CPU, optimized for Human Interface
Devices (HID) applications
— 256 Bytes of SRAM
— 8 Kbytes of Flash memory with EEPROM emulation
— In-System reprogrammable
— CPU speed up to 12 MHz
— 16-bit free-running timer
— Low power wakeup timer
— 12-bit Programmable Interval Timer with interrupts
— Watchdog timer
• Industry-Leading 2.4 GHz Radio Transceiver Function
— Operates in the unlicensed worldwide Industrial,
Scientific, and Medical (ISM) band
(2.4 GHz–2.483 GHz)
— DSSS data rates of up to 250 Kbps
— GFSK data rate of 1 Mbps
— –97 dBm receive sensitivity
PROC™ LP
CYRF69103
Block Diagram
VCC
CYRF69103
Programmable Radio on Chip
Low Power
— Programmable output power up to +4 dBm
— Auto Transaction Sequencer (ATS)
— Framing CRC and Auto ACK
— Received Signal Strength Indication (RSSI)
— Automatic Gain Control (AGC)
• Component Reduction
— Integrated 1.8V boost converter
— GPIOs that require no external components
— Operates off a single crystal
• Flexible I/O
— High current drive on GPIO pins. Configurable 8-mA or
50-mA/pin current sink on designated pins
— Each GPIO pin supports high-impedance inputs, config-
urable pull up, open drain output, CMOS/TTL inputs, and
CMOS output
— Maskable interrupts on all I/O pins
• Operating voltage from 1.8V to 3.6V DC
• Operating temperature from 0 to 70°C
• Lead-free 40-lead QFN package
• Advanced development tools based on Cypress’s PSoC®
tools
470nF
47µF
VCC
10µF
Microcontroller
Function
P0_2:4,7
4
P1_0:2,6:7
5
P2_0:1
2
P1.5/MOSI
P1.4/SCK
P1.3/nSS
RFbias
RFp
Radio
Function
RFn
IRQ/GPIO
MISO/GPIO
XOUT/GPIO
PACTL/GPIO
.....
12MHz
.......
470nF
Cypress Semiconductor Corporation
Document #: 001-07611 Rev *B
• 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Revised January 20, 2007
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CYRF69103
Data Transmission Modes and Data Rates
The SoC supports four different data transmission modes:
• In GFSK mode, data is transmitted at 1 Mbps, without any
DSSS.
• In 8DR mode, 8 bits are encoded in each
DATA_CODE_ADR derived code symbol transmitted.
• In DDR mode, 2-bits are encoded in each
DATA_CODE_ADR derived code symbol transmitted. (As
in the CYWUSB6934 DDR mode).
• In SDR mode, 1 bit is encoded in each DATA_CODE_ADR
derived code symbol transmitted. (As in the CYWUSB6934
standard modes.)
Both 64-chip and 32-chip DATA_CODE_ADR codes are
supported. The four data transmission modes apply to the data
after the SOP. In particular the length, data, and CRC16 are all
sent in the same mode. In general, lower data rates reduces
packet error rate in any given environment.
The CYRF69103 IC supports the following data rates:
• 1000-kbps (GFSK)
• 250-kbps (32-chip 8DR)
• 125-kbps (64-chip 8DR)
• 62.5-kbps (32-chip DDR)
• 31.25-kbps (64-chip DDR)
• 15.625-kbps (64-chip SDR)
Lower data rates typically provide longer range and/or a more
robust link.
Link Layer Modes
The CYRF69103 IC device supports the following data packet
framing features:
SOP – Packets begin with a 2-symbol Start of Packet (SOP)
marker. This is required in GFSK and 8DR modes, but is
optional in DDR mode and is not supported in SDR mode; if
framing is disabled then an SOP event is inferred whenever
two successive correlations are detected. The
SOP_CODE_ADR code used for the SOP is different from that
used for the “body” of the packet, and if desired may be a
different length. SOP must be configured to be the same
length on both sides of the link.
EOP – There are two options for detecting the end of a packet.
If SOP is enabled, then a packet length field may be enabled.
GFSK and 8DR must enable the length field. This is the first
8 bits after the SOP symbol, and is transmitted at the payload
data rate. If the length field is enabled, an End of Packet (EOP)
condition is inferred after reception of the number of bytes
defined in the length field, plus two bytes for the CRC16 (if
enabled—see below). The alternative to using the length field
is to infer an EOP condition from a configurable number of
successive non-correlations; this option is not available in
GFSK mode and is only recommended when using SDR
mode.
CRC16 – The device may be configured to append a 16-bit
CRC16 to each packet. The CRC16 uses the USB CRC
polynomial with the added programmability of the seed. If
enabled, the receiver will verify the calculated CRC16 for the
payload data against the received value in the CRC16 field.
The starting value for the CRC16 calculation is configurable,
and the CRC16 transmitted may be calculated using either the
loaded seed value or a zero seed; the received data CRC16
will be checked against both the configured and zero CRC16
seeds.
CRC16 detects the following errors:
• Any one bit in error
• Any two bits in error (no matter how far apart, which column,
and so on)
• Any odd number of bits in error (no matter where they are)
• An error burst as wide as the checksum itself
Figure 2 shows an example packet with SOP, CRC16 and
lengths fields enabled.
Figure 2. Example Default Packet Format
Preamble
n x 16us
2nd Framing
Symbol*
P
SOP 1
SOP 2
1st Framing
Symbol*
Length
Packet
length
1 Byte
Period
Payload Data
CRC 16
*Note:32 or 64us
Packet Buffers and Radio Configuration Registers
Packet data and configuration registers are accessed through
the SPI interface. All configuration registers are directly
addressed through the address field in the SPI packet (as in
the CYWUSB6934). Configuration registers are provided to
allow configuration of DSSS PN codes, data rate, operating
mode, interrupt masks, interrupt status, and others.
Packet Buffers
All data transmission and reception uses the 16-byte packet
buffers—one for transmission and one for reception.
The transmit buffer allows a complete packet of up to 16 bytes
of payload data to be loaded in one burst SPI transaction, and
then transmitted with no further MCU intervention. Similarly,
the receive buffer allows an entire packet of payload data up
to 16 bytes to be received with no firmware intervention
required until packet reception is complete.
Document #: 001-07611 Rev *B
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CYRF69103
Stack Pointer Register
Table 6. CPU Stack Pointer Register (CPU_SP)
Bit #
76543210
Field
Stack Pointer [7:0]
Read/Write
–
–
–
–
–
–
–
–
Default
00000
00
0
Bits 7:0
Stack Pointer [7:0]
8-bit data value holds a pointer to the current top-of-stack
CPU Program Counter High Register
Table 7. CPU Program Counter High Register (CPU_PCH)
Bit #
76543210
Field
Program Counter [15:8]
Read/Write
–
–
–
–
–
–
–
–
Default
00000
00
0
Bits 7:0
Program Counter [15:8]
8-bit data value holds the higher byte of the program counter
CPU Program Counter Low Register
Table 8. CPU Program Counter Low Register (CPU_PCL)
Bit #
76543210
Field
Program Counter [7:0]
Read/Write
–
–
–
–
–
–
–
–
Default
00000
00
0
Bit 7:0
Program Counter [7:0]
8-bit data value holds the lower byte of the program counter
Addressing Modes
Examples of the different addressing modes are discussed in
this section and example code is given.
Source Immediate
The result of an instruction using this addressing mode is
placed in the A register, the F register, the SP register, or the
X register, which is specified as part of the instruction opcode.
Operand 1 is an immediate value that serves as a source for
the instruction. Arithmetic instructions require two sources.
Instructions using this addressing mode are two bytes in
length.
Table 9. Source Immediate
Opcode
Instruction
Operand 1
Immediate Value
Examples
ADD A, 7
MOV X, 8
AND F, 9
;In this case, the immediate value
;of 7 is added with the Accumulator,
;and the result is placed in the
;Accumulator.
;In this case, the immediate value
;of 8 is moved to the X register.
;In this case, the immediate value
;of 9 is logically ANDed with the F
;register and the result is placed
;in the F register.
Source Direct
The result of an instruction using this addressing mode is
placed in either the A register or the X register, which is
specified as part of the instruction opcode. Operand 1 is an
address that points to a location in either the RAM memory
space or the register space that is the source for the
instruction. Arithmetic instructions require two sources; the
second source is the A register or X register specified in the
opcode. Instructions using this addressing mode are two bytes
in length.
Document #: 001-07611 Rev *B
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