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PDF DS80C400 Data sheet ( Hoja de datos )
| Número de pieza | DS80C400 | |
| Descripción | Network Microcontroller | |
| Fabricantes | Maxim Integrated Products | |
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GENERAL DESCRIPTION
The DS80C400 network microcontroller offers the highest
integration available in an 8051 device. Peripherals include
a 10/100 Ethernet MAC, three serial ports, a CAN 2.0B
controller, 1-Wire® Master, and 64 I/O pins.
To enable access to the network, a full application-
accessible TCP IPv4/6 network stack and OS are provided
in the ROM. The network stack supports up to 32
simultaneous TCP connections and can transfer up to
5Mbps through the Ethernet MAC. Its maximum system-
clock frequency of 75MHz results in a minimum instruction
cycle time of 54ns. Access to large program or data
memory areas is simplified with a 24-bit addressing
scheme that supports up to 16MB of contiguous memory.
To accelerate data transfers between the microcontroller
and memory, the DS80C400 provides four data pointers,
each of which can be configured to automatically increment
or decrement upon execution of certain data pointer-related
instructions. The DS80C400’s hardware math accelerator
further increases the speed of 32-bit and 16-bit multiply
and divide operations as well as high-speed shift,
normalization, and accumulate functions.
The High-Speed Microcontroller User’s Guide and the High-Speed
Microcontroller User’s Guide: Network Microcontroller Supplement
should be used in conjunction with this data sheet. Download
both at: www.maxim-ic.com/user_guides.
APPLICATIONS
Industrial Control/Automation
Environmental Monitoring
Network Sensors
Vending
Home/Office Automation
Data Converters (Serial-
to-Ethernet, CAN-to-
Ethernet)
Remote Data Collection
Equipment
Transaction/Payment
Terminals
ORDERING INFORMATION
PART
TEMP RANGE PIN-PACKAGE
DS80C400-FNY
-40°C to +85°C 100 LQFP
DS80C400-FNY+ -40°C to +85°C 100 LQFP
+ Denotes lead-free/RoHS-compliant device.
1-Wire is a registered trademark of Dallas Semiconductor Corp.
Magic Packet is a registered trademark of Advanced Micro
Devices, Inc.
DeviceNet is a trademark of Open DeviceNet Vendor Association, Inc.
EVALUATION KIT AVAILABLE
DS80C400
Network Microcontroller
FEATURES
High-Performance Architecture
Single 8051 Instruction Cycle in 54ns
DC to 75MHz Clock Rate
Flat 16MB Address Space
Four Data Pointers with Auto-Increment/
Decrement and Select-Accelerate Data Movement
16/32-Bit Math Accelerator
Multitiered Networking and I/O
10/100 Ethernet Media Access Controller (MAC)
CAN 2.0B Controller
1-Wire Net Controller
Three Full-Duplex Hardware Serial Ports
Up to Eight Bidirectional 8-Bit Ports (64 Digital I/O
Pins)
Robust ROM Firmware
Supports Network Boot Over Ethernet Using DHCP
and TFTP
Full, Application-Accessible TCP/IP Network Stack
Supports IPv4 and IPv6
Implements UDP, TCP, DHCP, ICMP, and IGMP
Preemptive, Priority-Based Task Scheduler
MAC Address can Optionally be Acquired from IEEE-
Registered DS2502-E48
10/100 Ethernet Mac
Flexible IEEE 802.3 MII (10/100Mbps) and ENDEC
(10Mbps) Interfaces Allow Selection of PHY
Low-Power Operation
Ultra-Low-Power Sleep Mode with Magic Packet®
and Wake-Up Frame Detection
8kB On-Chip Tx/Rx Packet Data Memory with Buffer
Control Unit Reduces Load on CPU
Half- or Full-Duplex Operation with Flow Control
Multicast/Broadcast Address Filtering with VLAN
Support
Full-Function CAN 2.0B Controller
15 Message Centers
Supports Standard (11-Bit) and Extended (29-Bit)
Identifiers and Global Masks
Media Byte Filtering to Support DeviceNet™, SDS, and
Higher Layer CAN Protocols
Auto-Baud Mode and SIESTA Low-Power Mode
Integrated Primary System Logic
16 Total Interrupt Sources with Six External
Four 16-Bit Timer/Counters
2x/4x Clock Multiplier Reduces Electromagnetic
Interference (EMI)
Programmable Watchdog Timer
Oscillator-Fail Detection
Programmable IrDA Clock
Features continued on page 32.
Pin Configuration appears at end of data sheet.
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.
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DS80C400 Network Microcontroller
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PARAMETER
SYMBOL
Data Float After RD (P3.7 or
PSEN) High
tRHDZ
ALE Low to Valid Data In
tLLDV
Port 0 Address to Valid Data
In
tAVDV0
Port 2, 4, 6 Address, Port 4
CE, or Port 5 PCE to Valid
Data In
tAVDV2
ALE Low to (RD or PSEN) or
WR Low
tLLWL
Port 0 Address to (RD or
PSEN) or WR Low
Port 2, 4 Address, Port 4 CE,
Port 5 PCE, to (RD or PSEN)
or WR Low
Data Valid to WR Transition
Data Hold After WR High
RD Low to Address Float
(RD or PSEN) or WR High to
ALE
(RD or PSEN) or WR High to
Port 4 CE or Port 5 PCE
High
tAVWL0
tAVWL2
tQVWX
tWHQX
tRLAZ
tWHLH
tWHLH2
MIN MAX
tCLCH - 3
tCLCL - 3
5tCLCL - 3
tCLCL - 5
2tCLCL - 6
10tCLCL - 6
tCLCL + tCLCH - 5
2tCLCL + tCLCH - 5
10tCLCL + tCLCH - 5
0
tCLCL - 4
2CLCL - 7
6tCLCL - 7
0
tCLCL - 3
5tCLCL - 3
tCHCL -5
tCLCL + tCHCL - 5
5tCLCL + tCHCL - 5
tCLCL - 5
2tCLCL - 5
6tCLCL - 5
2tCLCL + tCLCH - 19
(4 x CST + 1) tCLCL - 19
(4 x CST + 5) tCLCL - 19
3tCLCL - 19
(4 x CST + 2)tCLCL - 19
(4 x CST + 10)tCLCL - 19
3tCLCL + tCLCH - 19
(4 x CST + 2)tCLCL + tCLCH -
19
(4 x CST + 10)tCLCL + tCLCH -
20
tCLCH + 6
tCLCL + 6
5tCLCL + 6
(Note 2)
7
tCLCL + 4
5tCLCL + 4
tCHCL + 13
tCLCL + tCHCL + 13
5tCLCL + tCHCL + 13
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
STRETCH VALUES
CST (MD2:0)
CST = 0
1≤ CST ≤ 3
4 ≤ CST ≤ 7
CST = 0
1≤ CST ≤ 3
4 ≤ CST ≤ 7
CST = 0
1≤ CST ≤ 3
4 ≤ CST ≤ 7
CST = 0
1≤ CST ≤ 3
4 ≤ CST ≤ 7
CST = 0
1 ≤ CST ≤ 3
4 ≤ CST ≤ 7
CST = 0
1 ≤ CST ≤ 3
4 ≤ CST ≤ 7
CST = 0
1 ≤ CST ≤ 3
4 ≤ CST ≤ 7
CST = 0
1 ≤ CST ≤ 3
4 ≤ CST ≤ 7
0≤ CST ≤ 7
CST = 0
1 ≤ CST ≤ 3
4 ≤ CST ≤ 7
CST = 0
1 ≤ CST ≤ 3
4 ≤ CST ≤ 7
Note 1: Specifications to -40°C are guaranteed by design and not production tested.
Note 2: For a MOVX read operation, on the falling edge of ALE, Port 0 is held by a weak latch until overdriven by external memory.
Note 3: All parameters apply to both commercial and industrial temperature operation, unless otherwise noted.
Note 4: CST is the stretch cycle value as determined by the MD2, MD1, and MD0 bits of the CKCON register. tCLCL , tCLCH , tCHCL are time
periods associated with the internal system clock and are related to the external clock. See the System Clock Time Periods table.
Note 5: All signals characterized with load capacitance of 80pF except Port 0, Port 2, ALE, PSEN, RD, and WR with 100pF. The following
signals, when configured for memory interface, are also characterized with 100pF loading: Port 4 (CE0-3, A16–A19), Port 5.4–5.7
(PCE0-3), Port 6.0–6.5 (CE4-7, A20, A21), Port 7 (demultiplexed mode A0–A7).
Note 6: References to the XTAL, XTAL1, or CLK signal in timing diagrams are to assist in determining the relative occurrence of events, not for
determing absolute signal timing with respect to the external clock.
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DS80C400 Network Microcontroller
wwwM.DUataLSTheIPet4LUE.cXomED, 9-CYCLE DATA MEMORY PCE0-3 READ OR WRITE
PORT 4 – CE0 − 3
PORT 6 – CE4 − 7
PORT 4/6 ADDRESS
A16 -A21
A16 -A21
A16 -A21
MULTIPLEXED, 9-CYCLE DATA MEMORY CE0-7 READ
A16 -A21
PORT 4 – CE0 − 3
PORT 6 – CE4 − 7
PORT 4/6
ADDRESS
A16 -A21 A16 -A21
A16 -A21
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A16 -A21
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| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet DS80C400.PDF ] | |
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