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PDF STHDLS101 Data sheet ( Hoja de datos )
| Número de pieza | STHDLS101 | |
| Descripción | Level Translators | |
| Fabricantes | ST Microelectronics | |
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STHDLS101
AC coupled HDMI level shifter
Features
■ Converts low-swing alternating current (AC)
coupled differential input to high-definition
multimedia interface (HDMI) rev 1.3 compliant
■ HDMI level shifting operation up to 2.7 Gbps
per lane
■ Integrated 50 Ω termination resistors for
AC-coupled differential inputs
■ Input/output transition minimized differential
signaling (TMDS) enable/disable
■ Output slew rate control on TMDS outputs to
minimize electromagnetic interference (EMI)
■ Fail-safe outputs for backdrive protection
■ No re-timing or configuration required
■ Inter-pair output skew < 250 ps
■ Intra-pair output skew < 10 ps
■ Single power supply of 3.3 V
■ ESD protection: ±6 KV HBM on all I/O pins
■ Integrated display data channel (DDC) level
shifters. Pass-gate voltage limiters allow 3.3 V
termination on graphics and memory controller
hub (GMCH) pins and 5 V DDC termination on
HDMI connector pins
■ Hot-plug detect (HPD) signal level shifter from
HDMI/DVI connector
■ Integrated pull-down resistor on HPD_SINK
and OE_N inputs
Applications
■ Notebooks
■ PC motherboards and graphic cards
■ Dongles/cable adapters
QFN-48
(7 x 7 mm)
Description
The STHDLS101 is a high-speed high-definition
multimedia interface (HDMI) level shifter that
converts low-swing AC coupled differential input
to HDMI 1.3 compliant open-drain current
steering RX-terminated differential output.
Through the existing PCI-E pins in the graphics
and memory controller hub (GMCH) of PCs or
notebook motherboards, the pixel clock provides
the required bandwidth (1.65 Gbps, 2.25 Gbps)
for the video supporting 720p, 1080i, 1080p with a
total of 36-bit resolution. The HDMI is multiplexed
onto the PCIe pins in the motherboard where the
AC coupled HDMI at 1.2 V is output by GMCH.
The AC coupled HDMI is then level shifter by this
device to 3.3 V DC coupled HDMI output. The
STHDLS101 supports up to 2.7 Gbps, which is
enough for 12 bits of color depth per channel, as
indicated in HDMI rev 1.3. The device operates
from a single 3.3 V supply and is available in a
48-pin QFN package.
Table 1. Device summary
Order code
STHDLS101QTR
Package
QFN-48
Packing
Tape and reel
December 2008
Rev 4
1/25
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Figure 4. DP to HDMI/DVI cable adapter
System interface
HDMI/DVI
Transmitter
HPD
AC_TMDS
DDC
HPD_SOURCE
AC_TMDS
DDC
STHDLS101
HDMI/DVI Cable
Adaptor
HPD_SINK
DC TMDS
DDC
PC chipset
!-6
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4 Functional description
Functional description
This section describes the basic functionality of the STHDLS101 device.
Power supply
The STHDLS101 is powered by a single DC power supply of 3.3 V ± 10%.
Clocking
This device does not retime any data. The device contains no state machines. No inputs or
outputs of the device are latched or clocked.
Reset
This device acts as a level shifter, reset is not required.
OE_N function
When OE_N is asserted (low level), the IN_D and OUT_D signals are fully functional. Input
termination resistors are enabled and any internal bias circuits are turned on.
The OE_N pin has an internal pull-down that enables the chip if left unconnected.
When OE_N is de-asserted (high level), the OUT_D outputs are in high impedance state.
The IN_D input buffers are disabled and the IN_D termination resistors are disabled.
Internal bias circuits for the differential inputs and outputs are turned off. Power consumption
of the chip is minimized.
The HPD_SINK input and HPD_SOURCE output are not affected by OE_N. The SCL and
SDA pass-gates are not affected by OE_N.
Table 3. OE_N description
OE_N
Device state
Comments
Asserted Differential input buffers and output
(low level) buffers enabled. Input impedance =
or unconnected 50 Ω
De-asserted
(high level)
Low-power state.
Differential input buffers and
terminations are disabled. Differential
input buffers are in high-impedance
state.
OUT_D level shifting outputs are
disabled. OUT_D level shifting outputs
are in a high-impedance state.
Internal bias currents are turned off.
Normal functioning state for IN_D to
OUT_D level shifting function.
Intended for lowest power condition
when:
• No display is plugged in or
• The level shifted data path is disabled
HPD_SINK input and HPD_SOURCE
output are not affected by OE_N.
SCL_SOURCE, SCL_SINK,
SDA_SOURCE and SDA_SINK signals
and functions are not affected by OE_N.
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| Páginas | Total 25 Páginas | |
| PDF Descargar | [ Datasheet STHDLS101.PDF ] | |
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