|
|
PDF TDA9984A Data sheet ( Hoja de datos )
| Número de pieza | TDA9984A | |
| Descripción | HDMI 1.3 transmitter | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de TDA9984A (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
www.DataSheet4U.com
TDA9984A
HDMI 1.3 transmitter with 1080p upscaler embedded
Rev. 04 — 15 January 2009
Product data sheet
1. General description
The TDA9984A is a High-Definition Multimedia Interface (HDMI) v. 1.3 transmitter with
embedded 1080p upscaling functionality. It is backward compatible DVI 1.0 and can be
connected to any DVI 1.0 and HDMI sink. It allows mixing a 3 × 8-bit RGB or YCbCr video
stream with a pixel rate up to 150 MHz together with up to 4 × I2S-bus or one S/PDIF
audio streams with an audio sampling rate up to 192 kHz. It supports Gamut boundary
description (xvYCC), as well as HD audio, both HDMI 1.3 features.
A programmable upscaling block allows creating a 1080p output from a standard definition
input. An intrafield deinterlacer is included in the scaler.
In order to be compatible with most applications, and thanks to the integration of a fully
programmable input formatter and color space conversion block, the video input formats
accepted also include YCbCr 4 : 4 : 4 (up to 3 × 8-bit), YCbCr 4 : 2 : 2 semi-planar (up to
2 × 12-bit) and YCbCr 4 : 2 : 2 compliant with ITU656 (up to 1 × 12-bit). In case of
ITU656-like format, the input pixel clock can be made active on both edges.
The TDA9984A includes a HDCP 1.2 compliant cipher block. The HDCP key are stored
internally in a non-volatile OTP memory for maximum security.
The TDA9984A includes a true I2C-bus master interface for DDC-bus communication for
EDID purpose and HDCP purpose.
The TDA9984A can be controlled by an I2C-bus interface.
2. Features
I 3 × 8-bit video data input buses; CMOS and LV-TTL compatible
I Horizontal synchronization, vertical synchronization and data enable inputs or VREF,
HREF and FREF inputs which can be used for synchronization
I Pixel rate clock input can be made active on one or both edges; selectable via I2C-bus
I 4 × I2S-bus audio input channels, one S/PDIF channel; audio data rate up to 192 kHz
per input for both standards
I Dolby-True HD and DTS-HD High bit rate audio support through the use of the HBR
interface
I 250 MHz to 1.50 GHz TMDS transmitter operation
I Programmable input formatter and upsampler/interpolator allows input of any of the
4 : 4 : 4 or 4 : 2 : 2 semi-planar and 4 : 2 : 2 ITU656-like formats
1 page  
www.DNatXaSPheSete4Um.coicmonductors
7. Pinning information
TDA9984A
HDMI 1.3 transmitter with 1080p upscaler embedded
HSYNC/HREF 1
VSYNC/VREF 2
VPP 3
AP7 4
AP6 5
AP5 6
AP4 7
AP3 8
AP2 9
AP1 10
AP0 11
ACLK 12
VDDD(3V3) 13
VSSD 14
VSSA(PLL)(1V8) 15
VDDA(PLL)(1V8) 16
INT 17
HPD 18
DDC_SDA 19
DDC_SCL 20
TDA9984AHW
60 VSSC
59 VDDC(1V8)
58 VPB[6]
57 VPB[7]
56 VPC[0]
55 VPC[1]
54 VPC[2]
53 VPC[3]
52 VPC[4]
51 VPC[5]
50 VPC[6]
49 VPC[7]
48 VDDD(3V3)
47 VSSD
46 VSSA(PLL)(1V8)
45 VDDA(PLL)(1V8)
44 I2C_SDA
43 I2C_SCL
42 RST_N
41 A0
001aag597
Fig 2. Pin configuration
7.1 Pin description
Table 3. Pin description
Symbol
Pin
HSYNC/HREF 1
VSYNC/VREF 2
VPP 3
Type[1]
I
I
P
AP7 4 I
AP6 5 I
AP5 6 I
AP4 7 I
AP3 8 I
Description
horizontal synchronization or reference input
vertical synchronization or reference input
programming voltage for OTP memory; connect to
ground for digital core in normal operation
audio port 7 input
audio port 6 input
audio port 5 input
audio port 4 input
audio port 3 input
TDA9984A_4
Product data sheet
Rev. 04 — 15 January 2009
© NXP B.V. 2009. All rights reserved.
5 of 40
5 Page 
www.DNatXaSPheSete4Um.coicmonductors
TDA9984A
HDMI 1.3 transmitter with 1080p upscaler embedded
8.1.2.1 RGB 4 : 4 : 4 external sync input (rising edge)
Table 6. RGB 4 : 4 : 4 mapping
Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 45h; VIP_CNTRL_2 = 01h.
Video port A
Video port B
Video port C
Pin RGB 4 : 4 : 4 Pin RGB 4 : 4 : 4 Pin RGB 4 : 4 : 4
VPA[0]
B[0]
VPB[0]
G[0]
VPC[0]
R[0]
VPA[1]
B[1]
VPB[1]
G[1]
VPC[1]
R[1]
VPA[2]
B[2]
VPB[2]
G[2]
VPC[2]
R[2]
VPA[3]
B[3]
VPB[3]
G[3]
VPC[3]
R[3]
VPA[4]
B[4]
VPB[4]
G[4]
VPC[4]
R[4]
VPA[5]
B[5]
VPB[5]
G[5]
VPC[5]
R[5]
VPA[6]
B[6]
VPB[6]
G[6]
VPC[6]
R[6]
VPA[7]
B[7]
VPB[7]
G[7]
VPC[7]
R[7]
Control
Pin
HSYNC/HREF
VSYNC/VREF
DE/FREF
RGB 4 : 4 : 4
used
used
used
VCLK
HSYNC/HREF
CONTROL
INPUTS VSYNC/VREF
DE/FREF
VPA[7:0]
VPB[7:0]
VPC[7:0]
B0[7:0]
G0[7:0]
R0[7:0]
B1[7:0]
G1[7:0]
R1[7:0]
B2[7:0]
G2[7:0]
R2[7:0]
B3[7:0]
G3[7:0]
R3[7:0]
...
...
...
DE could also be generated from HSYNC/HREF and VSYNC/VREF
Fig 4. Pixel encoding RGB 4 : 4 : 4 external sync input (rising edge)
Bxxx[7:0]
Bxxx[7:0]
Gxxx[7:0]
Gxxx[7:0]
Rxxx[7:0]
Rxxx[7:0]
001aag380
TDA9984A_4
Product data sheet
Rev. 04 — 15 January 2009
© NXP B.V. 2009. All rights reserved.
11 of 40
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet TDA9984A.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| TDA9984A | HDMI 1.3 transmitter | NXP Semiconductors |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |