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PDF PSMN1R5-25YL Data sheet ( Hoja de datos )
| Número de pieza | PSMN1R5-25YL | |
| Descripción | N-channel TrenchMOS Logic Level FET | |
| Fabricantes | NXP Semiconductors | |
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PSMN1R5-25YL
N-channel TrenchMOS logic level FET
Rev. 01 — 16 June 2009
Product data sheet
1. Product profile
1.1 General description
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using TrenchMOS technology. This product is designed and qualified for use in
industrial and communications applications.
1.2 Features and benefits
High efficiency due to low switching
and conduction losses
Suitable for logic level gate drive
sources
1.3 Applications
Class-D amplifiers
DC-to-DC converters
Motor control
Server power supplies
1.4 Quick reference data
Table 1. Quick reference
Symbol Parameter
Conditions
Min Typ Max Unit
VDS drain-source voltage Tj ≥ 25 °C; Tj ≤ 150 °C
- - 25 V
ID drain current
Tmb = 25 °C; VGS = 10 V; [1] - - 100 A
see Figure 1;
Ptot total power
dissipation
Tmb = 25 °C; see Figure 2
- - 109 W
Dynamic characteristics
QGD
gate-drain charge VGS = 4.5 V; ID = 10 A;
VDS = 12 V; see Figure 14;
see Figure 15
- 9.2 - nC
QG(tot) total gate charge
VGS = 4.5 V; ID = 10 A;
VDS = 12 V; see Figure 14;
see Figure 15
- 36 - nC
Static characteristics
RDSon drain-source
on-state resistance
VGS = 10 V; ID = 15 A;
Tj = 25 °C
- 1.13 1.5 mΩ
[1] Continuous current is limited by package.
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PSMN1R5-25YL
N-channel TrenchMOS logic level FET
6. Characteristics
Table 6. Characteristics
Symbol Parameter
Static characteristics
V(BR)DSS drain-source
breakdown voltage
VGS(th)
gate-source threshold
voltage
IDSS
IGSS
RDSon
drain leakage current
gate leakage current
drain-source on-state
resistance
RG gate resistance
Dynamic characteristics
QG(tot)
total gate charge
QGS
QGS(th)
QGS(th-pl)
QGD
VGS(pl)
Ciss
Coss
Crss
td(on)
tr
td(off)
tf
gate-source charge
pre-threshold
gate-source charge
post-threshold
gate-source charge
gate-drain charge
gate-source plateau
voltage
input capacitance
output capacitance
reverse transfer
capacitance
turn-on delay time
rise time
turn-off delay time
fall time
Conditions
ID = 250 µA; VGS = 0 V; Tj = 25 °C
ID = 250 µA; VGS = 0 V; Tj = -55 °C
ID = 1 mA; VDS = VGS; Tj = 25 °C;
see Figure 11; see Figure 12
ID = 1 mA; VDS = VGS; Tj = 150 °C;
see Figure 12
ID = 1 mA; VDS = VGS; Tj = -55 °C;
see Figure 12
VDS = 25 V; VGS = 0 V; Tj = 25 °C
VDS = 25 V; VGS = 0 V; Tj = 150 °C
VGS = 16 V; VDS = 0 V; Tj = 25 °C
VGS = -16 V; VDS = 0 V; Tj = 25 °C
VGS = 4.5 V; ID = 15 A; Tj = 25 °C
VGS = 10 V; ID = 15 A; Tj = 150 °C;
see Figure 13
VGS = 10 V; ID = 15 A; Tj = 25 °C
f = 1 MHz
ID = 10 A; VDS = 12 V; VGS = 10 V;
see Figure 14; see Figure 15
ID = 0 A; VDS = 0 V; VGS = 10 V
ID = 10 A; VDS = 12 V; VGS = 4.5 V;
see Figure 14; see Figure 15
ID = 10 A; VDS = 12 V; VGS = 4.5 V;
see Figure 14; see Figure 15
VDS = 12 V; see Figure 14
VDS = 12 V; VGS = 0 V; f = 1 MHz;
Tj = 25 °C; see Figure 16
VDS = 12 V; RL = 0.5 Ω; VGS = 4.5 V;
RG(ext) = 4.7 Ω
Min Typ Max Unit
25 - - V
22 - - V
1.3 1.7 2.15 V
0.65 - - V
- - 2.45 V
- - 1 µA
- - 100 µA
- - 100 nA
- - 100 nA
-
1.61 2.2
mΩ
- - 2.6 mΩ
-
1.13 1.5
mΩ
- 0.77 - Ω
- 76 - nC
- 71 - nC
- 36 - nC
- 12.3 - nC
- 7.8 - nC
- 4.5 - nC
- 9.2 - nC
- 2.4 - V
- 4830 - pF
- 1280 - pF
- 465 - pF
- 50 - ns
- 97 - ns
- 72 - ns
- 36 - ns
PSMN1R5-25YL_1
Product data sheet
Rev. 01 — 16 June 2009
© NXP B.V. 2009. All rights reserved.
5 of 13
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PSMN1R5-25YL
N-channel TrenchMOS logic level FET
8. Revision history
Table 7. Revision history
Document ID
Release date
PSMN1R5-25YL_1
20090616
Data sheet status
Product data sheet
Change notice
-
Supersedes
-
PSMN1R5-25YL_1
Product data sheet
Rev. 01 — 16 June 2009
© NXP B.V. 2009. All rights reserved.
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