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PDF XRT83VL38 Data sheet ( Hoja de datos )
| Número de pieza | XRT83VL38 | |
| Descripción | Short-Haul Transceiver | |
| Fabricantes | Exar Corporation | |
| Logotipo |  |
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www.DataShAePeRt4IUL .2c0o0m9
XRT83VL38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. 1.0.0
GENERAL DESCRIPTION
The XRT83VL38 is a fully integrated Octal (eight
channel) long-haul and short-haul line interface unit
for T1 (1.544Mbps) 100, E1 (2.048Mbps) 75 or
120 or J1 110applications.
In long-haul applications the XRT83VL38 accepts
signals that have been attenuated from 0 to 36dB at
772kHz in T1 mode (equivalent of 0 to 6000 feet of
cable loss) or 0 to 43dB at 1024kHz in E1 mode.
In T1 applications, the XRT83VL38 can generate five
transmit pulse shapes to meet the short-haul Digital
Cross-Connect (DSX-1) template requirements as
well as for Channel Service Units (CSU) Line Build
Out (LBO) filters of 0dB, -7.5dB -15dB and -22.5dB
as required by FCC rules. It also provides
programmable transmit pulse generators for each
channel that can be used for output pulse shaping
allowing performance improvement over a wide
variety of conditions (The arbitrary pulse generators
are available in both T1 and E1 modes).
The XRT83VL38 provides both a parallel/serial Host
microprocessor interface as well as a Hardware
mode for programming and control.
Both the B8ZS and HDB3 encoding and decoding
functions are selectable as well as AMI. Two on-chip
crystal-less jitter attenuators with a 32 or 64 bit FIFO
can be placed in the receive and the transmit paths
with loop bandwidths of less than 3Hz. The
XRT83VL38 provides a variety of loop-back and
diagnostic features as well as transmit driver short
circuit detection and receive loss of signal monitoring.
It supports internal impedance matching for 75
100 110 and 120 for both transmitter and
receiver. In the absence of the power supply, the
transmit outputs and receive inputs are tri-stated
allowing for redundancy applications The chip
includes an integrated programmable clock multiplier
that can synthesize T1 or E1 master.
APPLICATIONS
T1 Digital Cross-Connects (DSX-1)
ISDN Primary Rate Interface
CSU/DSU E1/T1/J1 Interface
T1/E1/J1 LAN/WAN Routers
Public switching Systems and PBX Interfaces
T1/E1/J1 Multiplexer and Channel Banks
Features (See Page 2)
FIGURE 1. BLOCK DIAGRAM OF THE XRT83VL38 T1/E1/J1 LIU (HOST MODE)
MCLKE1
MCLKT1
TPOS_n/TDATA_n
TNEG_n/CODES_n
TCLK_n
RCLK_n
RNEG_n/LCV_n
RPOS_n/RDATA_n
RLOS_n
HW/HOST
WR_R/W
RD_DS
ALE_AS
CS
RDY_DTACK
INT
MASTER CLOCK SYNTHESIZER
One of Eight channels, CHANNEL_n - (n= 0:7)
QRSS
PATTERN
GENERATOR
HDB3/
B8ZS
ENCODER
TX/RX JITTER
ATTENUATOR
TAOS
ENABLE
TIMING
CONTROL
DFM
DRIVE
MONITOR
TX FILTER
& PULSE
SHAPER
LINE
DRIVER
QRSS ENABLE
QRSS
DETECTOR
NETWORK
LOOP
DETECTOR
REMOTE
LOOPBACK
DIGITAL
LOOPBACK
LOOPBACK
ENABLE
HDB3/
B8ZS
DECODER
TX/RX JITTER
ATTENUATOR
TIMING &
DATA
RECOVERY
LBO[3:0]
PEAK
DETECTOR
& SLICER
NLCD ENABLE
LOS
DETECTOR
AIS
DETECTOR
EQUALIZER
CONTROL
LOCAL
ANALOG
LOOPBACK
RX
EQUALIZER
TEST
MICROPROCESSOR CONTROLLER
MCLKOUT
DMO_n
TTIP_n
TRING_n
TXON_n
RTIP_n
RRING_n
ICT
PTS1
PTS2
D[7:0]
PCLK
A[7:0]
RESET
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
1 page  
XRT83VL38
www.DataShReEeVt4.U1..c0o.0m
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
GENERAL DESCRIPTION 1
Applications 1
Block Diagram of the XRT83VL38 T1/E1/J1 LIU (Host Mode) 1
Block Diagram of the XRT83VL38 T1/E1/J1 LIU (Hardware Mode) 2
Features 2
Ordering Information 3
Package Pin Out 4
PIN DESCRIPTION BY FUNCTION 5
Receive Sections 5
Transmitter Sections 7
Microprocessor Interface 11
jitter Attenuator 14
Clock Synthesizer 14
Alarm Functions/Redundancy Support 16
Power and Ground 19
FUNCTIONAL DESCRIPTION 22
Master Clock Generator 22
Two Input Clock Source 22
One Input Clock Source 22
Master Clock Generator 23
23
RECEIVER 23
Receiver Input 23
Receive Monitor Mode 24
Receiver Loss of Signal (RLOS) 24
Simplified Diagram of -15dB T1/E1 Short Haul Mode and RLOS Condition 24
Simplified Diagram of -29dB T1/E1 Gain Mode and RLOS Condition 25
Simplified Diagram of -36dB T1/E1 Long Haul Mode and RLOS Condition 25
Simplified Diagram of Extended RLOS mode (E1 Only) 26
Receive HDB3/B8ZS Decoder 26
Recovered Clock (RCLK) Sampling Edge 26
Receive Clock and Output Data Timing 27
Jitter Attenuator 27
Gapped Clock (JA Must be Enabled in the Transmit Path) 27
Maximum Gap Width for Multiplexer/Mapper Applications 27
Arbitrary Pulse Generator for T1 and e1 28
Arbitrary Pulse Segment Assignment 28
TRANSMITTER 28
Digital Data Format 28
Transmit Clock (TCLK) Sampling Edge 28
Transmit Clock and Input Data Timing 29
Transmit HDB3/B8ZS Encoder 29
Examples of HDB3 Encoding 29
Examples of B8ZS Encoding 29
29
Driver Failure Monitor (DMO) 30
Transmit Pulse Shaper & Line Build Out (LBO) circuit 30
I
5 Page 
www.DataShReEeVt4.U1..c0o.0m
XRT83VL38
OCTAL T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
SIGNAL NAME LEAD # TYPE
DESCRIPTION
Receive External Resistor Control Pins - Hardware mode
RXRES1 R10 I Receive External Resistor Control Pin 1:
RXRES0
V10
Receive External Resistor Control Pin 0:
These pins determine the value of the external Receive fixed resistor according to the
following table:
RXRES1
0
0
1
1
RXRES0
0
1
0
1
Required Fixed External
RX Resistor
No External Fixed Resistor
240
210
150
NOTE: These pins are internally pulled “Low” with a 50k resistor.
RCLKE J16 I Receive Clock Edge - Hardware mode
Set this pin “High” to sample RPOS_N/RNEG_n on the falling edge of RCLK_n. With
this pin tied “Low”, output data are updated on the rising edge of RCLK_n.
Microprocessor Type Select Input pin 1 - Host mode
µPTS1
J16
This pin along with µPTS2 (pin 128) is used to select the microprocessor type.
SEE”MICROPROCESSOR TYPE SELECT INPUT PINS - HOST MODE:”
ON PAGE 12.
NOTE: This pin is internally pulled “Low” with a 50k resistor.
TRANSMITTER SECTIONS
SIGNAL NAME LEAD # TYPE
DESCRIPTION
TCLKE L15 I Transmit Clock Edge - Hardware mode
Set this pin “High” to sample transmit input data on the rising edge of TCLK_n. With
this pin tied “Low”, input data are sampled on the falling edge of TCLK_n.
Microprocessor Type Select Input pin 2 - Host mode
µPTS2
L15
This pin along with µPTS1 (pin 133) selects the microprocessor type. SEE”MICRO-
PROCESSOR TYPE SELECT INPUT PINS - HOST MODE:” ON PAGE 12.
NOTE: This pin is internally pulled “Low” with a 50k resistor.
TTIP_0
TTIP_1
TTIP_2
TTIP_3
TTIP_4
TTIP_5
TTIP_6
TTIP_7
E3 O Transmitter Tip Output for Channel _0
Positive differential transmit output to the line.
G4 Transmitter Tip Output for Channel _1
F17 Transmitter Tip Output for Channel _2
C16 Transmitter Tip Output for Channel _3
R2 Transmitter Tip Output for Channel _4
N2 Transmitter Tip Output for Channel _5
N16 Transmitter Tip Output for Channel _6
P16 Transmitter Tip Output for Channel _7
7
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| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet XRT83VL38.PDF ] | |
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