|
|
PDF ISL8201M Data sheet ( Hoja de datos )
| Número de pieza | ISL8201M | |
| Descripción | High Efficiency DC/DC Module | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de ISL8201M (archivo pdf) en la parte inferior de esta página. Total 16 Páginas | ||
|
No Preview Available !
Data Sheet
October 28, 2014
ISL8201M
FN6657.3
10A, High Efficiency DC/DC Module
The ISL8201M is a 20V, 10A output current, variable output
step-down power supply. Included in the 15mmx15mm
package is a high performance PWM controller switching at
600kHz, power MOSFETs, an inductor, and all the passive
components required for complete DC/DC power solution.
The ISL8201M operates over an input voltage range of 1V to
20V and supports an output voltage range of 0.6V to 5V,
which is set by a single dividing resistor. This high efficiency
power module is capable of delivering 10A (17A peak) output
with up to 95% efficiency, needing no heat sinks or airflow to
meet power specifications. Only bulk input and output
capacitors are needed to finish the design. Utilizing
voltage-mode control, the output voltage can be precisely
regulated to as low as 0.6V with up to ±1% output voltage
regulation. The ISL8201M also features internal
compensation, internal soft-start, auto-recovery overcurrent
protection, an enable option, and pre-biased output start-up
capability.
The ISL8201M is packaged in a thermally enhanced, compact
(15mmx15mm) and low profile (3.5mm) overmolded QFN
Package Module suitable for automated assembly by
standard surface mount equipment. The ISL8201M is RoHS
compliant.
Typical Schematic
(+5V/+12V)
OR PVCC
(+6.5V TO 14.4V) CPVCC
PVCC
V IN
COMP/EN
P V C C VIN
(+4.5V TO +20V) VIN ISL8201M
VOUT
C INFB
PHASE
ISL8201M
RFB
ISEN
PGND
VOUT
FB
PGND
(+5V / +V1O2UVT)
1V.IN8 V
CIN 10A
COUT
VOUT
COUT R FB
4.87k
Features
• Complete Switch Mode Power Supply
• Bias Voltage Range from +4.5 to +14.4V
- Wide Input Voltage Range from 1V up to 20V (see
“Input Voltage Considerations” on page 11)
• 10A DC Output Current, 17A Peak Output Current
• Adjustable +0.6V to +5V Output Range
• Up to 95% Efficiency
• Simple Voltage Mode Control
• Fixed 600kHz Switching Frequency
• Fast Transient Response
• Enable Function Option
• Pre-biased Output Start-up Capability
• Internal Soft-Start
• Overcurrent Protection by Low-Side MOSFET rDS(ON)
Sensing (Non-Latching, Auto-Recovery)
• Small Footprint, Low Profile Surface Mount QFN Package
(15mmx15mmx3.5mm)
• RoHS Compliant
Applications
• Servers
• Industrial Equipment
• Point of Load Regulation
• Other General Purpose Step-Down DC/DC
• Telecom and Datacom Applications
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2009, 2010, 2014. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
1 page  
Electrical Specifications TA = +25°C. VIN = 12V, VOUT = 1.5V. CIN = 220µFx1, 10µF/Ceramicx2, COUT = 330µF (ESR = 10m),
22µF/Ceramicx3. (Continued)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
Internal Resistor Between VOUT and FB Pins
Disabled Threshold Voltage (COMP/EN)
Reference Voltage
Reference Voltage Tolerance
RFB-TI
VENDIS
VREF
(Note 7)
(Note 7)
0°C to +70°C (Note 7)
9.66 9.76 9.85
0.375 0.4 0.425
- 0.6 -
-1.0 - +1.0
k
V
V
%
-40°C to +85°C (Note 7)
-1.5 - +1.5 %
FAULT PROTECTION
Internal Resistor Between ISET and PGND Pins RSET-IN
ISET Current Source
ISET (Note 7)
NOTE:
7. Parameters are 100% tested for internal IC prior to module assembly.
- 3.57 -
18.0 21.5 23.5
k
µA
Typical Performance Characteristics
Efficiency Performance
100
TA = +25°C, VIN = PVCC (PVCC = 5V for 18VIN), CIN = 220µFx1, 10µF/Ceramicx2, COUT = 330µF (ESR = 10m),
22µF/Ceramicx3. The efficiency equation is:
Efficiency
=
O------u---t---p---u----t----P-----o----w-----e----r
Input Power
=
-P----O----U----T--
PIN
=
---V----O--V---U-I--N-T----xx---II--OI--N--U-----T----
100
90 90
80 80
70
3.3V
60 2.5V
1.5V
50 1.2V
0.8V
40
70
60
5.0V
3.3V 2.5V
1.5V
50 1.2V
0.8V
40
30
0 2 4 6 8 10
LOAD CURRENT (A)
FIGURE 2. EFFICIENCY vs LOAD CURRENT (5VIN)
30
0 2 4 6 8 10
LOAD CURRENT (A)
FIGURE 3. EFFICIENCY vs LOAD CURRENT (12VIN)
100
90
80
5.0V
70 3.3V
2.5V
60
1.5V
50 1.2V
40
30
0 2 4 6 8 10
LOAD CURRENT (A)
FIGURE 4. EFFICIENCY vs LOAD CURRENT (18VIN)
VIN = 12V
VOUT = 1.2V
IOUT = 0A to 5A
FIGURE 5. 1.2V TRANSIENT RESPONSE
Submit Document Feedback
5
FN6657.3
October 28, 2014
5 Page 
1. The maximum rDS(ON) at the highest junction
temperature
2. The minimum ISET from the “Electrical Specifications”
table on page 3.
3. Determine IPEAK for:
IPEAK
IO
UT
MAX
+
-------I--L----
2
(EQ. 4)
where IL is the output inductor ripple current. In a high input
voltage, high output voltage application, such as 20V input to
5V output, the inductor ripple becomes excessive due to the
fixed internal inductor value. In such applications, the output
current will be limited from the rating to approximately 70%
of the module’s rated current.
The relationships between the external RSET values and the
typical output current IOUT(MAX) OCP levels are as follows:
TABLE 2.
RSET
()
OPEN
OCP (A) AT VIN = 12V,
PVCC = 5V
13.3
OCP (A) AT VIN = 12V
PVCC = 12V
17.3
50k 12.6
16.6
20k 11.4
14.9
10k 10.2
13.3
5k 7.6
10.3
3k 6.3
8.3
2k 4.9
6.7
The range of allowable voltages detected (2 x ISET x RSET) is
0mV to 475mV. If the voltage drop across RSET is set too
low, then this can cause almost continuous OCP tripping and
retry. It will also be very sensitive to system noise and
in-rush current spikes, so it should be avoided. The
maximum usable setting is around 0.2V across RSET (0.4V
across the MOSFET); values above this might disable the
protection. Any voltage drop across RSET that is greater than
0.3V (0.6V MOSFET trip point) will disable the OCP. Note
that conditions during power-up or during a retry may look
different than normal operation. During power-up in a 12V
system, the ISL8201M starts operation just above 4V; if the
supply ramp is slow, the soft-start ramp might be over well
before 12V is reached. Therefore, with low-side gate drive
voltages, the rDS(ON) of the MOSFET will be higher during
power-up, effectively lowering the OCP trip. In addition, the
ripple current will likely be different at a lower input voltage.
Another factor is the digital nature of the soft-start ramp. On
each discrete voltage step, there is in effect, a small load
transient and a current spike to charge the output capacitors.
The height of the current spike is not controlled, however, it
is affected by the step size of the output and the value of the
output capacitors, as well as the internal error amp
compensation. Therefore, it is possible to trip the overcurrent
with in-rush current, in addition to the normal load and ripple
considerations.
Submit Document Feedback
11
Figure 19 shows the output response during a retry of an
output shorted to PGND. At time t0, the output has been
turned off due to sensing an overcurrent condition. There are
two internal soft-start delay cycles (t1 and t2) to allow the
MOSFETs to cool down in order to keep the average power
dissipation in retry at an acceptable level. At time t2, the
output starts a normal soft-start cycle, and the output tries to
ramp. If the short is still applied and the current reaches the
ISET trip point any time during the soft-start ramp period, the
output will shut off and return to time t0 for another delay
cycle. The retry period is thus two dummy soft-start cycles
plus one variable one (which depends on how long it takes to
trip the sensor each time). Figure 19 shows an example
where the output gets about half-way up before shutting
down; therefore, the retry (or hiccup) time will be around
17ms. The minimum should be nominally 13.6ms and the
maximum 20.4ms. If the short condition is finally removed,
the output should ramp up normally on the next t2 cycle.
t0 t1
t2
VOUT
FIGURE 19. OVERCURRENT RETRY OPERATION
Starting up into a shorted load looks the same as a retry into
that same shorted load. In both cases, OCP is always
enabled during soft-start; once it trips, it will go into retry
(hiccup) mode. The retry cycle will always have two dummy
time-outs, plus whatever fraction of the real soft-start time
passes before the detection and shutoff. At that point, the
logic immediately starts a new two dummy cycle time-out.
Input Voltage Considerations
Figure 12 shows a standard configuration where PVCC is
either 5V (±10%) or 12V (±20%). In each case, the gate
drivers use the PVCC voltage for low-side gate and high-side
gate driver. In addition, PVCC is allowed to work anywhere
from 6.5V up to the 14.4V maximum. The PVCC range
between 5.5V and 6.5V is not allowed for long-term reliability
reasons, but transitions through it to voltages above 6.5V are
acceptable.
There is an internal 5V regulator for bias, which turns on
between 5.5V and 6.5V. Some of the delay after POR is there
to allow a typical power supply to ramp-up past 6.5V before
FN6657.3
October 28, 2014
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet ISL8201M.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| ISL8201M | High Efficiency DC/DC Module | Intersil Corporation |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |