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PDF PI7C9X130 Data sheet ( Hoja de datos )

Número de pieza PI7C9X130
Descripción PCI Express-to-PCI Reversible Bridge
Fabricantes Pericom Semiconductor Corporation　
Logotipo Pericom Semiconductor Corporation Logotipo



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PI7C9X130
PCI Express to PCI-X
Reversible Bridge
Revision 1.2
3545 North First Street, San Jose, CA 95134
Telephone: 1-877-PERICOM, (1-877-737-4266)
Fax: 408-435-1100
Internet: http://www.pericom.com

1 page




PI7C9X130 pdf
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PI7C9X130
PCI EXPRESS TO PCI-X BRIDGE
TABLE OF CONTENTS
1 INTRODUCTION .............................................................................................................................................13
1.1 PCI EXPRESS FEATURES........................................................................................................................13
1.2 PCI/PCI-X FEATURES ..............................................................................................................................14
1.3 GENERAL FEATURES .............................................................................................................................14
2 PIN DEFINITION .............................................................................................................................................15
2.1 SIGNAL TYPES .........................................................................................................................................15
2.2 PCI EXPRESS SIGNALS ...........................................................................................................................15
2.3 PCI SIGNALS .............................................................................................................................................16
2.4 MODE SELECT AND STRAPPING SIGNALS........................................................................................18
2.5 JTAG BOUNDARY SCAN SIGNALS.......................................................................................................18
2.6 MISCELLANEOUS SIGNALS ..................................................................................................................19
2.7 POWER AND GROUND PINS ..................................................................................................................20
2.8 PIN ASSIGNMENT ....................................................................................................................................20
3 MODE SELECTION AND PIN STRAPPING ...............................................................................................22
3.1 FUNCTIONAL MODE SELECTION ........................................................................................................22
3.2 PCI/PCI-X SELECTION.............................................................................................................................22
3.3 PIN STRAPPING ........................................................................................................................................23
4 FORWARD AND REVERSE BRIDGING .....................................................................................................24
5 TRANSPARENT AND NON-TRANSPARENT BRIDGING .......................................................................25
5.1 TRANSPARENT MODE ............................................................................................................................25
5.2 NON-TRANSPARENT MODE ..................................................................................................................26
6 PCI EXPRESS FUNCTIONAL OVERVIEW ................................................................................................27
6.1 TLP STRUCTURE......................................................................................................................................27
6.2 VIRTUAL ISOCHRONOUS OPERATION ...............................................................................................28
7 CONFIGURATION REGISTERS...................................................................................................................29
7.1 CONFIGURATION REGISTER MAP.......................................................................................................29
7.2 PCI EXPRESS EXTENDED CAPABILITY REGISTER MAP.................................................................34
7.3 CONTROL AND STATUS REGISTER MAP ...........................................................................................35
7.4 PCI CONFIGURATION REGISTERS FOR TRANSPARENT BRIDGE MODE.....................................37
7.4.1 VENDOR ID – OFFSET 00h ...............................................................................................................37
7.4.2 DEVICE ID – OFFSET 00h.................................................................................................................37
7.4.3 COMMAND REGISTER – OFFSET 04h.............................................................................................37
7.4.4 PRIMARY STATUS REGISTER – OFFSET 04h..................................................................................38
7.4.5 REVISION ID REGISTER – OFFSET 08h ..........................................................................................40
7.4.6 CLASS CODE REGISTER – OFFSET 08h..........................................................................................40
7.4.7 CACHE LINE SIZE REGISTER – OFFSET 0Ch.................................................................................40
7.4.8 PRIMARY LATENCY TIMER REGISTER – OFFSET 0Ch .................................................................40
7.4.9 HEADER TYPE REGISTER – OFFSET 0Ch ......................................................................................41
7.4.10 RESERVED REGISTERS – OFFSET 10h TO 17h ..............................................................................41
7.4.11 PRIMARY BUS NUMBER REGISTER – OFFSET 18h .......................................................................41
7.4.12 SECONDARY BUS NUMBER REGISTER – OFFSET 18h .................................................................41
7.4.13 SUBORDINATE BUS NUMBER REGISTER – OFFSET 18h .............................................................41
7.4.14 SECONDARY LATENCY TIMER REGISTER – OFFSET 18h............................................................41
7.4.15 I/O BASE REGISTER – OFFSET 1Ch.................................................................................................41
7.4.16 I/O LIMIT REGISTER – OFFSET 1Ch................................................................................................42
PERICOM SEMICONDUCTOR
Page 5 of 157
September 2007 - Rev 1.2

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PI7C9X130 arduino
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PI7C9X130
PCI EXPRESS TO PCI-X BRIDGE
7.6.20
7.6.21
7.6.22
7.6.23
7.6.24
7.6.25
7.6.26
7.6.27
7.6.28
7.6.29
7.6.30
7.6.31
7.6.32
7.6.33
7.6.34
7.6.35
7.6.36
7.6.37
PRIMARY SET IRQ REGISTER - OFFSET 074h..............................................................................136
SECONDARY SET IRQ REGISTER - OFFSET 074h........................................................................136
PRIMARY CLEAR IRQ MASK REGISTER - OFFSET 078h.............................................................137
SECONDARY CLEAR IRQ MASK REGISTER - OFFSET 078h .......................................................137
PRIMARY SET IRQ MASK REGISTER - OFFSET 07Ch..................................................................137
SECONDARY SET IRQ MASK REGISTER - OFFSET 07Ch............................................................137
RESERVED REGISTERS – OFFSET 080h TO 09Ch........................................................................138
SCRATCHPAD 0 REGISTER - OFFSET 0A0h .................................................................................138
SCRATCHPAD 1 REGISTER - OFFSET 0A4h .................................................................................138
SCRATCHPAD 2 REGISTER - OFFSET 0A8h .................................................................................138
SCRATCHPAD 3 REGISTER - OFFSET 0ACh.................................................................................138
SCRATCHPAD 4 REGISTER - OFFSET 0B0h .................................................................................139
SCRATCHPAD 5 REGISTER - OFFSET 0B4h .................................................................................139
SCRATCHPAD 6 REGISTER - OFFSET 0B8h .................................................................................139
SCRATCHPAD 7 REGISTER - OFFSET 0BCh.................................................................................139
RESERVED REGISTERS – OFFSET 0C0h TO 0FCh.......................................................................139
LOOKUP TABLE REGISTERS – OFFSET 100h TO 1FCh ..............................................................140
RESERVED REGISTERS – OFFSET 200h TO FFCh .......................................................................140
8 GPIO PINS AND SM BUS ADDRESS ..........................................................................................................141
9 CLOCK SCHEME ..........................................................................................................................................142
10 INTERRUPTS .............................................................................................................................................142
11 EEPROM (I2C) INTERFACE AND SYSTEM MANAGEMENT BUS.................................................144
11.1 EEPROM (I2C) INTERFACE...................................................................................................................144
11.2 SYSTEM MANAGEMENT BUS .............................................................................................................144
12 HOT PLUG OPERATION .........................................................................................................................144
13 RESET SCHEME........................................................................................................................................145
14 IEEE 1149.1 COMPATIBLE JTAG CONTROLLER.............................................................................146
14.1 INSTRUCTION REGISTER.....................................................................................................................146
14.2 BYPASS REGISTER ................................................................................................................................146
14.3 DEVICE ID REGISTER ...........................................................................................................................146
14.4 BOUNDARY SCAN REGISTER .............................................................................................................147
14.5 JTAG BOUNDARY SCAN REGISTER ORDER....................................................................................147
15 POWER MANAGEMENT .........................................................................................................................152
16 ELECTRICAL AND TIMING SPECIFICATIONS ................................................................................153
16.1 ABSOLUTE MAXIMUM RATINGS.......................................................................................................153
16.2 DC SPECIFICATIONS .............................................................................................................................153
16.3 AC SPECIFICATIONS .............................................................................................................................154
17 PACKAGE INFORMATION.....................................................................................................................155
18 ORDERING INFORMATION...................................................................................................................157
PERICOM SEMICONDUCTOR
Page 11 of 157
September 2007 - Rev 1.2

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